Code Review / openocd.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | review | tree
raw | inline | side by side
target: create/use register_cache_invalidate()
[openocd.git] / src / target / xscale.c
diff --git a/src/target/xscale.c b/src/target/xscale.c
index a4a8eabd6111dc92b70eda31c3fbeb08649def71..f13366ac0b95f331c32d86531b7742b2db0bea71 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -857,7 +857,7 @@ static int xscale_arch_state(struct target *target)
                        "%s",
                         armv4_5_state_strings[armv4_5->core_state],
                         Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-                        armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
+                        arm_mode_name(armv4_5->core_mode),
                         buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
                         buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
                         state[xscale->armv4_5_mmu.mmu_enabled],
@@ -954,13 +954,14 @@ static int xscale_debug_entry(struct target *target)
        LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 
        armv4_5->core_mode = buffer[9] & 0x1f;
-       if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
+       if (!is_arm_mode(armv4_5->core_mode))
        {
                target->state = TARGET_UNKNOWN;
                LOG_ERROR("cpsr contains invalid mode value - communication failure");
                return ERROR_TARGET_FAILURE;
        }
-       LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
+       LOG_DEBUG("target entered debug state in %s mode",
+                        arm_mode_name(armv4_5->core_mode));
 
        if (buffer[9] & 0x20)
                armv4_5->core_state = ARMV4_5_STATE_THUMB;
@@ -968,9 +969,6 @@ static int xscale_debug_entry(struct target *target)
                armv4_5->core_state = ARMV4_5_STATE_ARM;
 
 
-       if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
-               return ERROR_FAIL;
-
        /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
        if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
        {
@@ -1324,7 +1322,7 @@ static int xscale_resume(struct target *target, int current,
        if (!debug_execution)
        {
                /* registers are now invalid */
-               armv4_5_invalidate_core_regs(target);
+               register_cache_invalidate(armv4_5->core_cache);
                target->state = TARGET_RUNNING;
                target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
        }
@@ -1403,8 +1401,7 @@ static int xscale_step_inner(struct target *target, int current,
        target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 
        /* registers are now invalid */
-       if ((retval = armv4_5_invalidate_core_regs(target)) != ERROR_OK)
-               return retval;
+       register_cache_invalidate(armv4_5->core_cache);
 
        /* wait for and process debug entry */
        if ((retval = xscale_debug_entry(target)) != ERROR_OK)
@@ -1540,7 +1537,7 @@ static int xscale_deassert_reset(struct target *target)
                breakpoint = breakpoint->next;
        }
 
-       armv4_5_invalidate_core_regs(target);
+       register_cache_invalidate(xscale->armv4_5_common.core_cache);
 
        /* FIXME mark hardware watchpoints got unset too.  Also,
         * at least some of the XScale registers are invalid...
@@ -3132,16 +3129,13 @@ COMMAND_HANDLER(xscale_handle_mmu_command)
 
        if (CMD_ARGC >= 1)
        {
-               if (strcmp("enable", CMD_ARGV[0]) == 0)
-               {
+               bool enable;
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+               if (enable)
                        xscale_enable_mmu_caches(target, 1, 0, 0);
-                       xscale->armv4_5_mmu.mmu_enabled = 1;
-               }
-               else if (strcmp("disable", CMD_ARGV[0]) == 0)
-               {
+               else
                        xscale_disable_mmu_caches(target, 1, 0, 0);
-                       xscale->armv4_5_mmu.mmu_enabled = 0;
-               }
+               xscale->armv4_5_mmu.mmu_enabled = enable;
        }
 
        command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
@@ -3153,10 +3147,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 {
        struct target *target = get_current_target(CMD_CTX);
        struct xscale_common *xscale = target_to_xscale(target);
-       int icache = 0, dcache = 0;
-       int retval;
 
-       retval = xscale_verify_pointer(CMD_CTX, xscale);
+       int retval = xscale_verify_pointer(CMD_CTX, xscale);
        if (retval != ERROR_OK)
                return retval;
 
@@ -3166,38 +3158,28 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
                return ERROR_OK;
        }
 
-       if (strcmp(CMD_NAME, "icache") == 0)
-               icache = 1;
-       else if (strcmp(CMD_NAME, "dcache") == 0)
-               dcache = 1;
+       bool icache;
+       COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
 
        if (CMD_ARGC >= 1)
        {
-               if (strcmp("enable", CMD_ARGV[0]) == 0)
-               {
-                       xscale_enable_mmu_caches(target, 0, dcache, icache);
-
-                       if (icache)
-                               xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
-                       else if (dcache)
-                               xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
-               }
-               else if (strcmp("disable", CMD_ARGV[0]) == 0)
-               {
-                       xscale_disable_mmu_caches(target, 0, dcache, icache);
-
-                       if (icache)
-                               xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
-                       else if (dcache)
-                               xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-               }
+               bool enable;
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
+               if (enable)
+                       xscale_enable_mmu_caches(target, 1, 0, 0);
+               else
+                       xscale_disable_mmu_caches(target, 1, 0, 0);
+               if (icache)
+                       xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
+               else
+                       xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
        }
 
-       if (icache)
-               command_print(CMD_CTX, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
-
-       if (dcache)
-               command_print(CMD_CTX, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+       bool enabled = icache ?
+                                       xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
+                                       xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
+       const char *msg = enabled ? "enabled" : "disabled";
+       command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
 
        return ERROR_OK;
 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)