XScale: better {read,write}_phys()

[openocd.git] / src / target / xscale.c

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 1acaba0765f21863cb2b1016ad24f39c9beab4b2..f1afc71f127102b7c0edc342a8773576a0713e84 100644 (file)
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -36,6 +36,8 @@
 #include <helper/time_support.h>
 #include "register.h"
 #include "image.h"
+#include "arm_opcodes.h"
+#include "armv4_5.h"
 
 
 /*
@@ -857,21 +859,14 @@ static int xscale_arch_state(struct target *target)
                "", "\n(processor reset)", "\n(trace buffer full)"
        };
 
-       if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+       if (armv4_5->common_magic != ARM_COMMON_MAGIC)
        {
                LOG_ERROR("BUG: called for a non-ARMv4/5 target");
                return ERROR_INVALID_ARGUMENTS;
        }
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-                       "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-                       "MMU: %s, D-Cache: %s, I-Cache: %s"
-                       "%s",
-                        armv4_5_state_strings[armv4_5->core_state],
-                        Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-                        arm_mode_name(armv4_5->core_mode),
-                        buf_get_u32(armv4_5->cpsr->value, 0, 32),
-                        buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+       arm_arch_state(target);
+       LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
                         state[xscale->armv4_5_mmu.mmu_enabled],
                         state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
                         state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
@@ -1429,7 +1424,7 @@ static int xscale_step_inner(struct target *target, int current,
 static int xscale_step(struct target *target, int current,
                uint32_t address, int handle_breakpoints)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
        struct breakpoint *breakpoint = target->breakpoints;
 
        uint32_t current_pc;
@@ -1501,7 +1496,7 @@ static int xscale_assert_reset(struct target *target)
        xscale_write_dcsr(target, 1, 0);
 
        /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
-       xscale_jtag_set_instr(target->tap, 0x7f);
+       xscale_jtag_set_instr(target->tap, ~0);
        jtag_execute_queue();
 
        /* assert reset */
@@ -1658,7 +1653,7 @@ static int xscale_deassert_reset(struct target *target)
 }
 
 static int xscale_read_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode)
+               int num, enum arm_mode mode)
 {
        /** \todo add debug handler support for core register reads */
        LOG_ERROR("not implemented");
@@ -1666,7 +1661,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int xscale_write_core_reg(struct target *target, struct reg *r,
-               int num, enum armv4_5_mode mode, uint32_t value)
+               int num, enum arm_mode mode, uint32_t value)
 {
        /** \todo add debug handler support for core register writes */
        LOG_ERROR("not implemented");
@@ -1675,7 +1670,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
 
 static int xscale_full_context(struct target *target)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
 
        uint32_t *buffer;
 
@@ -1697,11 +1692,11 @@ static int xscale_full_context(struct target *target)
         */
        for (i = 1; i < 7; i++)
        {
-               enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+               enum arm_mode mode = armv4_5_number_to_mode(i);
                bool valid = true;
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are invalid registers in the current mode
@@ -1724,7 +1719,7 @@ static int xscale_full_context(struct target *target)
                /* get banked registers:  r8 to r14; and SPSR
                 * except in USR/SYS mode
                 */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        /* SPSR */
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
@@ -1757,7 +1752,7 @@ static int xscale_full_context(struct target *target)
 
 static int xscale_restore_banked(struct target *target)
 {
-       struct arm *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_arm(target);
 
        int i, j;
 
@@ -1774,10 +1769,10 @@ static int xscale_restore_banked(struct target *target)
         */
        for (i = 1; i < 7; i++)
        {
-               enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+               enum arm_mode mode = armv4_5_number_to_mode(i);
                struct reg *r;
 
-               if (mode == ARMV4_5_MODE_USR)
+               if (mode == ARM_MODE_USR)
                        continue;
 
                /* check if there are dirty registers in this mode */
@@ -1789,7 +1784,7 @@ static int xscale_restore_banked(struct target *target)
                }
 
                /* if not USR/SYS, check if the SPSR needs to be written */
-               if (mode != ARMV4_5_MODE_SYS)
+               if (mode != ARM_MODE_SYS)
                {
                        if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16).dirty)
@@ -1817,7 +1812,7 @@ dirty:
                }
 
                /* send spsr if not in USR/SYS mode */
-               if (mode != ARMV4_5_MODE_SYS) {
+               if (mode != ARM_MODE_SYS) {
                        r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                        mode, 16);
                        xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
@@ -1910,7 +1905,13 @@ static int xscale_read_memory(struct target *target, uint32_t address,
 static int xscale_read_phys_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
-       /** \todo: provide a non-stub implementtion of this routine. */
+       struct xscale_common *xscale = target_to_xscale(target);
+
+       /* with MMU inactive, there are only physical addresses */
+       if (!xscale->armv4_5_mmu.mmu_enabled)
+               return xscale_read_memory(target, address, size, count, buffer);
+
+       /** \todo: provide a non-stub implementation of this routine. */
        LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
                        target_name(target), __func__);
        return ERROR_FAIL;
@@ -1997,7 +1998,13 @@ static int xscale_write_memory(struct target *target, uint32_t address,
 static int xscale_write_phys_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
-       /** \todo: provide a non-stub implementtion of this routine. */
+       struct xscale_common *xscale = target_to_xscale(target);
+
+       /* with MMU inactive, there are only physical addresses */
+       if (!xscale->armv4_5_mmu.mmu_enabled)
+               return xscale_read_memory(target, address, size, count, buffer);
+
+       /** \todo: provide a non-stub implementation of this routine. */
        LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
                        target_name(target), __func__);
        return ERROR_FAIL;
@@ -2607,7 +2614,7 @@ static int xscale_read_instruction(struct target *target,
                return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
        }
 
-       if (xscale->trace.core_state == ARMV4_5_STATE_ARM)
+       if (xscale->trace.core_state == ARM_STATE_ARM)
        {
                uint8_t buf[4];
                if ((retval = image_read_section(xscale->trace.image, section,
@@ -2620,7 +2627,7 @@ static int xscale_read_instruction(struct target *target,
                opcode = target_buffer_get_u32(target, buf);
                arm_evaluate_opcode(opcode, xscale->trace.current_pc, instruction);
        }
-       else if (xscale->trace.core_state == ARMV4_5_STATE_THUMB)
+       else if (xscale->trace.core_state == ARM_STATE_THUMB)
        {
                uint8_t buf[2];
                if ((retval = image_read_section(xscale->trace.image, section,
@@ -2672,7 +2679,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
                int rollover;
                int branch;
                int exception;
-               xscale->trace.core_state = ARMV4_5_STATE_ARM;
+               xscale->trace.core_state = ARM_STATE_ARM;
 
                chkpt = 0;
                rollover = 0;
@@ -2806,7 +2813,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
                                        }
                                        else
                                        {
-                                               xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2;
+                                               xscale->trace.current_pc += (xscale->trace.core_state == ARM_STATE_ARM) ? 4 : 2;
                                        }
                                        command_print(cmd_ctx, "%s", instruction.text);
                                }
@@ -2821,7 +2828,7 @@ static int xscale_analyze_trace(struct target *target, struct command_context *c
                        }
                }
 
-               for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARMV4_5_STATE_ARM) ? 4 : 2)
+               for (; xscale->trace.current_pc < trace_data->last_instruction; xscale->trace.current_pc += (xscale->trace.core_state == ARM_STATE_ARM) ? 4 : 2)
                {
                        struct arm_instruction instruction;
                        if ((retval = xscale_read_instruction(target, &instruction)) != ERROR_OK)
@@ -2859,7 +2866,7 @@ static void xscale_build_reg_cache(struct target *target)
        int i;
        int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
 
-       (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+       (*cache_p) = arm_build_reg_cache(target, armv4_5);
 
        (*cache_p)->next = malloc(sizeof(struct reg_cache));
        cache_p = &(*cache_p)->next;
@@ -2975,6 +2982,9 @@ static int xscale_init_arch_info(struct target *target,
        xscale->dbr0_used = 0;
        xscale->dbr1_used = 0;
 
+       LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
+                       target_name(target));
+
        xscale->arm_bkpt = ARMV5_BKPT(0x0);
        xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 
@@ -2992,7 +3002,7 @@ static int xscale_init_arch_info(struct target *target,
        armv4_5->write_core_reg = xscale_write_core_reg;
        armv4_5->full_context = xscale_full_context;
 
-       armv4_5_init_arch_info(target, armv4_5);
+       arm_init_arch_info(target, armv4_5);
 
        xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
        xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
@@ -3721,7 +3731,7 @@ struct target_type xscale_target =
        .deassert_reset = xscale_deassert_reset,
        .soft_reset_halt = NULL,
 
-       .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
        .read_memory = xscale_read_memory,
        .read_phys_memory = xscale_read_phys_memory,