tcl: [1/3] prepare for jimtcl 0.81 'expr' syntax change

[openocd.git] / tcl / board / at91sam9261-ek.cfg

diff --git a/tcl/board/at91sam9261-ek.cfg b/tcl/board/at91sam9261-ek.cfg
index 3963e9373d81dea38edb753572645bbc5ce3a73e..d6e8c2d15475c915618e6ce0330852af24575427 100644 (file)
--- a/tcl/board/at91sam9261-ek.cfg
+++ b/tcl/board/at91sam9261-ek.cfg
@@ -30,29 +30,29 @@ proc at91sam9261ek_reset_init { } {
        ;# set master_pll_mul   13
 
        set val [expr $::AT91_WDT_WDV]                  ;# Counter Value
-       set val [expr ($val | $::AT91_WDT_WDDIS)]       ;# Watchdog Disable
-       set val [expr ($val | $::AT91_WDT_WDD)]         ;# Delta Value
-       set val [expr ($val | $::AT91_WDT_WDDBGHLT)]    ;# Debug Halt
-       set val [expr ($val | $::AT91_WDT_WDIDLEHLT)]   ;# Idle Halt
+       set val [expr {$val | $::AT91_WDT_WDDIS}]       ;# Watchdog Disable
+       set val [expr {$val | $::AT91_WDT_WDD}]         ;# Delta Value
+       set val [expr {$val | $::AT91_WDT_WDDBGHLT}]    ;# Debug Halt
+       set val [expr {$val | $::AT91_WDT_WDIDLEHLT}]   ;# Idle Halt
 
        set config(wdt_mr_val) $val
 
        ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
        set config(matrix_ebicsa_addr)  $::AT91_MATRIX_EBICSA
-       set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+       set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
 
        ;# SDRAMC_CR - Configuration register
        set val [expr $::AT91_SDRAMC_NC_9]
-       set val [expr ($val | $::AT91_SDRAMC_NR_13)]
-       set val [expr ($val | $::AT91_SDRAMC_NB_4)]
-       set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
-       set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
-       set val [expr ($val | (2 <<  8))]               ;# Write Recovery Delay
-       set val [expr ($val | (7 << 12))]               ;# Row Cycle Delay
-       set val [expr ($val | (3 << 16))]               ;# Row Precharge Delay
-       set val [expr ($val | (2 << 20))]               ;# Row to Column Delay
-       set val [expr ($val | (5 << 24))]               ;# Active to Precharge Delay
-       set val [expr ($val | (8 << 28))]               ;# Exit Self Refresh to Active Delay
+       set val [expr {$val | $::AT91_SDRAMC_NR_13}]
+       set val [expr {$val | $::AT91_SDRAMC_NB_4}]
+       set val [expr {$val | $::AT91_SDRAMC_CAS_3}]
+       set val [expr {$val | $::AT91_SDRAMC_DBW_32}]
+       set val [expr {$val | (2 <<  8)}]               ;# Write Recovery Delay
+       set val [expr {$val | (7 << 12)}]               ;# Row Cycle Delay
+       set val [expr {$val | (3 << 16)}]               ;# Row Precharge Delay
+       set val [expr {$val | (2 << 20)}]               ;# Row to Column Delay
+       set val [expr {$val | (5 << 24)}]               ;# Active to Precharge Delay
+       set val [expr {$val | (8 << 28)}]               ;# Exit Self Refresh to Active Delay
 
        set config(sdram_cr_val) $val