#
# source [find target/...cfg]
-# Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of
-# the AT91SAM9260 and shares the same tap ID as it.
+source [find target/at91sam9g20.cfg]
-set _CHIPNAME at91sam9g20
set _FLASHTYPE nandflash_cs3
-set _ENDIAN little
-set _CPUTAPID 0x0792603f
# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore
# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is
reset_config srst_only
-# Set up the CPU and generate a new jtag tap for AT91SAM9G20.
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Use caution changing the delays listed below. These seem to be
-# affected by the board and type of JTAG adapter. A value of 200 ms seems
-# to work reliably for the configuration listed in the file header above.
-
adapter_nsrst_delay 200
jtag_ntrst_delay 200
-# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
-
-jtag_rclk 5
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
-# Both areas are 16 kB long.
-
-#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
-
# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
# some powerful features, we want to have a special function that handles "reset init". To do this we declare
proc read_register {register} {
set result ""
- ocd_mem2array result 32 $register 1
+ mem2array result 32 $register 1
return $result(0)
}
# jtag speed without causing GDB keep alive problem.
arm7_9 fast_memory_access disable
- adapter_khz 2 # Slow-speed oscillator enabled at reset, so run jtag speed slow.
- halt # Make sure processor is halted, or error will result in following steps.
+ adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+ halt ;# Make sure processor is halted, or error will result in following steps.
wait_halt 10000
- mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset.
+ mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
}
proc at91sam9g20_reset_init { } {
# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog.
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
# a number of registers. The first step involves setting up the general I/O pins on the processor
# to be able to interface and support the external memory.
- mww 0xfffffc10 0x00000010 # PMC_PCER : enable PIOC clock
- mww 0xfffff800 0x00006000 # PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
- mww 0xfffff810 0x00004000 # PIOC_OER : enable output on 14
- mww 0xfffff814 0x00002000 # PIOC_ODR : disable output on 13
- mww 0xfffff830 0x00004000 # PIOC_SODR : set 14 to disable NAND
+ mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
# The exact physical timing characteristics for the memory type used on the current board
# (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
# is a little tedious to do here. If you have questions about how to do this, Atmel has
# a decent application note #6255B that covers this process.
- mww 0xffffec30 0x00020002 # SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
- mww 0xffffec34 0x04040404 # SMC_PULSE3 : 4 clock cycle pulse for all signals
- mww 0xffffec38 0x00070006 # SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
- mww 0xffffec3C 0x00020003 # SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+ mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+ mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+ mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
- mww 0xffffe800 0x00000001 # ECC_CR : reset the ECC parity registers
- mww 0xffffe804 0x00000002 # ECC_MR : page size is 2112 words (word is 8 bits)
+ mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
# Identify NandFlash bank 0.
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