rename jtag_khz as adapter_khz

[openocd.git] / tcl / board / at91sam9g20-ek.cfg

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index b0fe54620258b8c34c83d256b4c0ed9024863365..f24f1a13d895186f329233dbf376f8bf80f9d4aa 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -28,8 +28,9 @@ reset_config trst_and_srst
 
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-# Use caution changing the delays listed below.  These seem to be affected by the board and type of
-# debugger dongle.  A value of 200 ms seems to work reliably for the configuration listed in the file header above.
+# Use caution changing the delays listed below.  These seem to be
+# affected by the board and type of JTAG adapter.  A value of 200 ms seems
+# to work reliably for the configuration listed in the file header above.
 
 jtag_nsrst_delay 200
 jtag_ntrst_delay 200
@@ -76,7 +77,7 @@ proc at91sam9g20_init { } {
        # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
        # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
 
-       jtag_khz 2                      # Slow-speed oscillator enabled at reset, so run jtag speed slow.
+       adapter_khz 2                   # Slow-speed oscillator enabled at reset, so run jtag speed slow.
        halt                            # Make sure processor is halted, or error will result in following steps.
        mww 0xfffffd08 0xa5000501       # RSTC_MR : enable user reset.
        mww 0xfffffd44 0x00008000       # WDT_MR : disable watchdog.
@@ -111,7 +112,7 @@ proc at91sam9g20_init { } {
 
        # Switch over to adaptive clocking.
 
-       jtag_khz 0
+       adapter_khz 0
 
        # Enable faster DCC downloads.