-################################################################################\r
-# Atmel AT91SAM9260-EK eval board\r
-#\r
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933\r
-#\r
-# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz\r
-# OSCSEL configured for external 32.768 kHz crystal\r
-#\r
-# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks\r
-#\r
-################################################################################\r
-\r
-# We add to the minimal configuration.\r
-source [find target/at91sam9260.cfg]\r
-\r
-# By default S1 is open and this means that NTRST is not connected.\r
-# The reset_config in target/at91sam9260.cfg is overridden here.\r
-# (or S1 must be populated with a 0 Ohm resistor)\r
-reset_config srst_only\r
-\r
-$_TARGETNAME configure -event reset-start {\r
- # At reset CPU runs at 32.768 kHz.\r
- # JTAG Frequency must be 6 times slower if RCLK is not supported.\r
- jtag_rclk 5\r
- halt\r
- # RSTC_MR : enable user reset, MMU may be enabled... use physical address\r
- arm926ejs mww_phys 0xfffffd08 0xa5000501\r
-}\r
- \r
-$_TARGETNAME configure -event reset-init {\r
- mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog\r
-\r
- mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator\r
- sleep 20 # wait 20 ms\r
- mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator\r
- sleep 10 # wait 10 ms\r
- mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz\r
- sleep 20 # wait 20 ms\r
- mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)\r
- sleep 10 # wait 10 ms\r
- mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)\r
- sleep 10 # wait 10 ms\r
-\r
- # Increase JTAG Speed to 6 MHz if RCLK is not supported\r
- jtag_rclk 6000\r
-\r
- arm7_9 dcc_downloads enable # Enable faster DCC downloads\r
-\r
- mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31\r
- mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31\r
- \r
- mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory\r
-\r
- mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)\r
-\r
- mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x4\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command\r
- mww 0x20000000 0\r
- mww 0xffffea00 0x0 # SDRAMC_MR : normal mode\r
- mww 0x20000000 0\r
- mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us\r
-}\r
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+# OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+ # At reset CPU runs at 32.768 kHz.
+ # JTAG Frequency must be 6 times slower if RCLK is not supported.
+ jtag_rclk 5
+ halt
+ # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+ mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+ mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
+
+ mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+ sleep 20 ;# wait 20 ms
+ mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
+ sleep 10 ;# wait 10 ms
+ mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+ sleep 10 ;# wait 10 ms
+
+ # Increase JTAG Speed to 6 MHz if RCLK is not supported
+ jtag_rclk 6000
+
+ arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
+
+ mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
+ mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
+
+ mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+ mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+ mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
+ mww 0x20000000 0
+ mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x4
+ mww 0x20000000 0
+ mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
+ mww 0x20000000 0
+ mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
+ mww 0x20000000 0
+ mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
+}
Code Review / openocd.git / blobdiff