jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / tcl / board / hitex_lpc2929.cfg

diff --git a/tcl/board/hitex_lpc2929.cfg b/tcl/board/hitex_lpc2929.cfg
index d2515371df806f4c6cfc6f550aa8dc11eb0820eb..35007c06550dcfc0d64076431bb7aa37623ac005 100644 (file)
--- a/tcl/board/hitex_lpc2929.cfg
+++ b/tcl/board/hitex_lpc2929.cfg
@@ -1,13 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 # Hitex eval board for LPC2929/LPC2939
 # http://www.hitex.com/
 
 # Delays on reset lines
-adapter_nsrst_delay 50
+adapter srst delay 50
 jtag_ntrst_delay 1
 
 # Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
 # Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
+adapter speed 2000
 
 # Target device: LPC29xx with ETB
 # The following variables are used by the LPC2900 script:
@@ -24,7 +26,7 @@ $_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-
 # Event handlers
 $_TARGETNAME configure -event reset-start {
   # Back to the slow JTAG clock
-  adapter_khz 2000
+  adapter speed 2000
 }
 
 # External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
@@ -34,7 +36,7 @@ flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
 
 $_TARGETNAME configure -event reset-init {
   # Flash
-  mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not chached
+  mww 0x20200010 0x00000007     ;# FBWST: 7 wait states, not cached
 
   # Use PLL
   mww 0xFFFF8020 0x00000001     ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
@@ -46,7 +48,7 @@ $_TARGETNAME configure -event reset-init {
   mww 0xFFFF8070 0x02000000     ;# SYS_CLK_CONF: PLL
 
   # Increase JTAG speed
-  adapter_khz 6000
+  adapter speed 6000
 
   # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
   mww 0xE0001138 0x0000001F     ;# P1.14 = D0
@@ -103,4 +105,3 @@ $_TARGETNAME configure -event reset-init {
   mww 0x600000CC 0x0000000C     ;# Bank7 WST2=8
   mww 0x600000C4 0x00000002     ;# Bank7 IDCY=2
 }
-