TCL/SPEAr: remove code to autodetect DDR

[openocd.git] / tcl / chip / st / spear / spear3xx_ddr.tcl

diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index 14b5dfe05f15b3a6ab229254ab4db09d64406bfb..a9787d11d4c8d206ae3166976be2c495e47ba749 100644 (file)
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -6,23 +6,26 @@
 # Author:    Antonio Borneo <borneo.antonio@gmail.com>
 
 
-proc sp3xx_ddr_init {ddr_type} {
+proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
+       if { $ddr_chips != 1 && $ddr_chips != 2 } {
+               error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
+       }
+
        if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
-               ddr_spr3xx_mt47h64m16_3_333_cl5_async
+               ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
                set ddr_size 0x08000000
        ## add here new DDR chip definition. Prototype:
        #} elseif { $ddr_type == "?????" } {
-       #       ?????
+       #       ????? $ddr_chips
        #       set ddr_size 0x?????
        } else {
                error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
        }
 
-       # Check for single/double memory chip
-       # DDR starts at address 0x00000000
-       mww $ddr_size 0x87654321
-       mww 0x00000000 0x12345678
-       if {[expr [mrw 0x00000000] == 0x12345678 && [mrw $ddr_size] == 0x87654321]} {
+       # MPMC START
+       mww 0xfc60001c 0x01000100
+
+       if { $ddr_chips == 2 } {
                echo [format \
                        "Double chip DDR memory. Total memory size 0x%08x byte" \
                        [expr 2 * $ddr_size]]
@@ -35,7 +38,7 @@ proc sp3xx_ddr_init {ddr_type} {
 
 
 # from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
-proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
+proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
        # DDR_PAD_REG
        mww 0xfca800f0 0x00003aa5
 
@@ -53,9 +56,15 @@ proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
        mww 0xfc600018 0x00010001       ;# MEMCTL_GP_02
        mww 0xfc60001c 0x00000100       ;# MEMCTL_GP_03
        mww 0xfc600020 0x00010001       ;# MEMCTL_GP_04
-       mww 0xfc600024 0x01020203       ;# MEMCTL_GP_05
-       mww 0xfc600028 0x01000102       ;# MEMCTL_GP_06
-       mww 0xfc60002c 0x02000202       ;# MEMCTL_AHB_SET_02
+       if { $ddr_chips == 2 } {
+               mww 0xfc600024 0x01020203       ;# MEMCTL_GP_05
+               mww 0xfc600028 0x01000102       ;# MEMCTL_GP_06
+               mww 0xfc60002c 0x02000202       ;# MEMCTL_AHB_SET_02
+       } else {
+               mww 0xfc600024 0x00000201       ;# MEMCTL_GP_05
+               mww 0xfc600028 0x02000001       ;# MEMCTL_GP_06
+               mww 0xfc60002c 0x02000201       ;# MEMCTL_AHB_SET_02
+       }
        mww 0xfc600030 0x04040105       ;# MEMCTL_AHB_SET_03
        mww 0xfc600034 0x03030302       ;# MEMCTL_AHB_SET_04
        mww 0xfc600038 0x02040101       ;# MEMCTL_AHB_SET_05
@@ -115,6 +124,4 @@ proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {} {
        mww 0xfc6001a8 0x00000000       ;# MEMCTL_LWPWR_REG
        mww 0xfc6001ac 0x00860000       ;# MEMCTL_GP_15
        mww 0xfc6001b0 0x00000002       ;# MEMCTL_TPDEX
-       # MPMC START
-       mww 0xfc60001c 0x01000100
 }