tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

[openocd.git] / tcl / memory.tcl

diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index 219d39fa79e7a04579cb48c4f2ebb6e278289695..8d50ba8531ae50acd323ffa5b10f6a6a6ea0ab21 100644 (file)
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -1,4 +1,4 @@
-# MEMORY 
+# MEMORY
 #
 # All Memory regions have two components.
 #    (1) A count of regions, in the form N_NAME
@@ -43,9 +43,9 @@ set RWX_NO_ACCESS     0
 set RWX_X_ONLY        $BIT0
 set RWX_W_ONLY        $BIT1
 set RWX_R_ONLY        $BIT2
-set RWX_RW            [expr $RWX_R_ONLY + $RWX_W_ONLY]
-set RWX_R_X           [expr $RWX_R_ONLY + $RWX_X_ONLY]
-set RWX_RWX           [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY]
+set RWX_RW            [expr {$RWX_R_ONLY + $RWX_W_ONLY}]
+set RWX_R_X           [expr {$RWX_R_ONLY + $RWX_X_ONLY}]
+set RWX_RWX           [expr {$RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY}]
 set UNKNOWN(0,RWX)     $RWX_NO_ACCESS
 
 #     WIDTH       - access width
@@ -54,15 +54,15 @@ set ACCESS_WIDTH_NONE 0
 set ACCESS_WIDTH_8    $BIT0
 set ACCESS_WIDTH_16   $BIT1
 set ACCESS_WIDTH_32   $BIT2
-set ACCESS_WIDTH_ANY  [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32]
+set ACCESS_WIDTH_ANY  [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32}]
 set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
 
 proc iswithin { ADDRESS BASE LEN } {
-    return [expr ((($ADDRESS - $BASE) > 0) && (($ADDRESS - $BASE + $LEN) > 0))]
+    return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
 }
 
 proc address_info { ADDRESS } {
-    
+
     foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
        if { info exists $WHERE } {
            set lmt [set N_[set WHERE]]
@@ -80,54 +80,108 @@ proc address_info { ADDRESS } {
 
 proc memread32 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 32 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 32 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread32: $msg"
     }
-}    
+}
 
 proc memread16 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 16 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 16 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread16: $msg"
     }
-}    
+}
 
 proc memread8 {ADDR} {
     set foo(0) 0
-    if ![ catch { ocd_mem2array foo 8 $ADDR 1  } msg ] {
+    if ![ catch { mem2array foo 8 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memread8: $msg"
     }
-}    
+}
 
 proc memwrite32 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 32 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 32 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memwrite32: $msg"
     }
-}    
+}
 
 proc memwrite16 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 16 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 16 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memwrite16: $msg"
     }
-}    
+}
 
 proc memwrite8 {ADDR DATA} {
     set foo(0) $DATA
-    if ![ catch { ocd_array2mem foo 8 $ADDR 1  } msg ] {
+    if ![ catch { array2mem foo 8 $ADDR 1  } msg ] {
        return $foo(0)
     } else {
        error "memwrite8: $msg"
     }
-}    
+}
+
+proc memread32_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread32: $msg"
+    }
+}
+
+proc memread16_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread16: $msg"
+    }
+}
+
+proc memread8_phys {ADDR} {
+    set foo(0) 0
+    if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memread8: $msg"
+    }
+}
+
+proc memwrite32_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite32: $msg"
+    }
+}
+
+proc memwrite16_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite16: $msg"
+    }
+}
+
+proc memwrite8_phys {ADDR DATA} {
+    set foo(0) $DATA
+    if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
+       return $foo(0)
+    } else {
+       error "memwrite8: $msg"
+    }
+}