mips32: pracc: Fix UPPER/LOWER macros

[openocd.git] / tcl / target / amdm37x.cfg

diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index 6004070f7b1a96a3994b93c5016fcecc1e01bae3..5c4e3151d3c4b2587f14654d98982b86ccf80329 100644 (file)
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -33,7 +33,7 @@ if { [info exists CHIPTYPE] } {
       }
       am35x {
          # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
-         set _JRC_TAPID "-expected-id 0x0b7ae02f"
+         set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
       }
       default {
          error "ERROR: CHIPTYPE was set, but it was not set to a valid value.  Acceptable values are \"dm37x\" or \"am35x\"."
@@ -50,7 +50,7 @@ adapter_khz 10
 ###############################################################################
 # JTAG setup
 # The OpenOCD commands are described in the TAP Declaration section
-#  http://openocd.sourceforge.net/doc/html/TAP-Declaration.html
+#  http://openocd.org/doc/html/TAP-Declaration.html
 ###############################################################################
 
 # The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
@@ -61,7 +61,7 @@ source [find target/icepick.cfg]
 
 # The TAP order should be described from the TDO connection in OpenOCD to the
 #  TDI pin.  The OpenOCD FAQ describes this in more detail:
-#  http://openocd.sourceforge.net/doc/html/FAQ.html
+#  http://openocd.org/doc/html/FAQ.html
 
 # From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
 #
@@ -86,8 +86,8 @@ source [find target/icepick.cfg]
 
 # Secondary TAP: DAP is closest to the TDO output
 # The TAP enable event also needs to be described
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
+jtag configure $_CHIPNAME.cpu -event tap-enable \
    "icepick_c_tapenable $_CHIPNAME.jrc 3"
 
 # These taps are only present in the DM37x series.
@@ -136,12 +136,13 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
 ###############################################################################
 # Target Setup:
 # This section is described in the OpenOCD documentation under CPU Configuration
-#  http://openocd.sourceforge.net/doc/html/CPU-Configuration.html
+#  http://openocd.org/doc/html/CPU-Configuration.html
 ###############################################################################
 
 # Create the CPU target to be used with GDB:  Cortex-A8, using DAP
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
 
 # The DM37x has 64K of SRAM starting at address 0x4020_0000.  Allow the first
 # 16K to be used as a scratchpad for OpenOCD.
@@ -199,7 +200,7 @@ $_TARGETNAME configure -event gdb-attach {
 # Run this to enable invasive debugging.  This is run automatically in the
 # reset sequence.
 proc amdm37x_dbginit {target} {
-   # General Cortex A8 debug initialisation
+   # General Cortex-A8 debug initialisation
    cortex_a dbginit
 
    # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but