puts "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
}
-# mrw,mmw from davinci.cfg
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
- set value ""
- ocd_mem2array value 32 $reg 1
- return $value(0)
-}
+source [find mem_helper.tcl]
# read a 64-bit register (memory mapped)
proc mr64bit {reg} {
set value ""
- ocd_mem2array value 32 $reg 2
+ mem2array value 32 $reg 2
return $value
}
mww [expr $reg+4] $high
}
-# mmw: "memory modify word", updates value of $reg
-# $reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
- set old [mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww $reg $new
-}
-
proc showNOR {} {
puts "This is the current NOR setup"
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
- ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+ mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
- ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+ mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
# see if the PLL is in bypass mode
set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
puts [format "PLL bypass bit: %d" $bypass]
if {$tmp == "128M"} {
configureDDR2regs_128M
} elseif {$tmp == "256M"} {
- configureDDR2regs_256B
+ configureDDR2regs_256M
} else {
puts "Don't know how to configure DDR2 setup?"
}
# */
# mov r0, #0
# mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr 15 0 7 7 0 0x0
+ arm mcr 15 0 7 7 0 0x0
# mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- mcr 15 0 8 7 0 0x0
+ arm mcr 15 0 8 7 0 0x0
# /*
# * disable MMU stuff and caches
# */
# mrc p15, 0, r0, c1, c0, 0
- mrc 15 0 1 0 0
+ arm mrc 15 0 1 0 0
# bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
# bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
# orr r0, r0, #0x00000002 @ set bit 2 (A) Align
# orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
# orr r0, r0, #0x00400000 @ set bit 22 (U)
# mcr p15, 0, r0, c1, c0, 0
- mcr 15 0 1 0 0 0x401002
+ arm mcr 15 0 1 0 0 0x401002
# This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
# APB init
# // Setting APB Bus Wait states to 1, set post write
mww $INTC_ARM1_CONTROL_REG 0x1
# configure clocks
setupPLL
+ # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
+ setupUART0
# enable cache
# ? (u-boot does nothing here)
# DDR2 memory init
setupDDR2
- setupUART0
putsUART0 "C100 initialization complete.\n"
puts "C100 initialization complete."
}
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
puts "JTAG speed lowered to 100kHz"
- jtag_khz 100
+ adapter_khz 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
puts -nonewline "Wating for watchdog to trigger..."