tcl/esp32s3: check memory protection on gdb attach

[openocd.git] / tcl / target / esp32s3.cfg

diff --git a/tcl/target/esp32s3.cfg b/tcl/target/esp32s3.cfg
index 0570501c750ec30022e91e97f803dc533fa41b7b..967c3a2d1017154c131de5de0a83b4617044b6e2 100644 (file)
--- a/tcl/target/esp32s3.cfg
+++ b/tcl/target/esp32s3.cfg
@@ -39,7 +39,50 @@ if { $_ONLYCPU != 1 } {
 }
 
 proc esp32s3_memprot_is_enabled { } {
-       # TODO: after https://review.openocd.org/c/openocd/+/7016 merged
+       # SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C1124 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C11D0 0] != 0 } {
+               return 1
+       }
+       # IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10D8 0] != 0 } {
+               return 1
+       }
+       # DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+       if { [get_mmr_bit 0x600C10FC 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C10E4 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C10F0 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1104 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1114 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C119C 0] != 0 } {
+               return 1
+       }
+       # SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
+       if { [get_mmr_bit 0x600C1248 0] != 0 } {
+               return 1
+       }
        return 0
 }
 
@@ -56,13 +99,13 @@ $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
 
 $_TARGETNAME_0 configure -event gdb-attach {
        $_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
-       # necessary to auto-probe flash bank when GDB is connected
+       # necessary to auto-probe flash bank when GDB is connected and generate proper memory map
        halt 1000
        if { [esp32s3_memprot_is_enabled] } {
                # 'reset halt' to disable memory protection and allow flasher to work correctly
                echo "Memory protection is enabled. Reset target to disable it..."
                reset halt
-    }
+       }
 }
 $_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }