tcl/target/gd32vf103: add flash bank

[openocd.git] / tcl / target / gd32vf103.cfg

diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg
index 0f4dcf375e8759b1f3e9b07a735534d2ee565648..cfc64783f772bcb4b5718f8082d36ed73cdc1b10 100644 (file)
--- a/tcl/target/gd32vf103.cfg
+++ b/tcl/target/gd32vf103.cfg
@@ -4,6 +4,8 @@
 # https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
 #
 
+source [find mem_helper.tcl]
+
 transport select jtag
 
 if { [info exists CHIPNAME] } {
@@ -12,10 +14,11 @@ if { [info exists CHIPNAME] } {
    set _CHIPNAME gd32vf103
 }
 
+# The smallest RAM size 6kB (GD32VF103C4/T4/R4)
 if { [info exists WORKAREASIZE] } {
    set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x800
+   set _WORKAREASIZE 0x1800
 }
 
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
@@ -24,3 +27,14 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# DBGMCU_CR register cannot be set in examine-end event as the running RISC-V CPU
+# does not allow the debugger to access memory.
+# Stop watchdogs at least before flash programming.
+$_TARGETNAME configure -event reset-init {
+       # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
+       mmw 0xE0042004 0x00000300 0
+}