icepick-d: extend access to core control register

[openocd.git] / tcl / target / icepick.cfg

diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 36ffc022c6f7f0bda2979294a2556c22dfc3cacb..0f160bb1073c2342391c3ba5cd9c373b8ad83730 100644 (file)
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -63,7 +63,8 @@ proc icepick_c_router {jrc rw block register payload} {
        irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
 
        # ROUTER instructions are 32 bits wide
-       set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+       set old_dr_value 0x[drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
+#      echo "\tOld router value:\t0x[format %x $old_dr_value]"
 }
 
 # Configure the icepick control register
@@ -107,11 +108,17 @@ proc icepick_c_tapenable {jrc port} {
        runtest 10
 }
 
+# jrc  == TAP name for the ICEpick
+# coreid== core id number 0..15 (not same as port number!)
+proc icepick_d_set_core_control {jrc coreid value } {
+       icepick_c_router $jrc 1 0x6 $coreid $value
+}
+
 # jrc  == TAP name for the ICEpick
 # port == a port number, 0..15
 # Follow the sequence described in
 # http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
-proc icepick_d_tapenable {jrc port} {
+proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
        # First CONNECT to the ICEPick
        icepick_c_connect $jrc
        icepick_c_setup $jrc
@@ -119,9 +126,8 @@ proc icepick_d_tapenable {jrc port} {
        # Select the port
        icepick_c_router $jrc 1 0x2 $port 0x2108
 
-       # Set 4 bit core ID to the Cortex-A
-       irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
-       drscan $jrc 32 0xe0002008 -endstate DRPAUSE
+       # Set icepick core control for $coreid
+       icepick_d_set_core_control $jrc $coreid $value
 
        # Enter the bypass state
        irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE