cfg: LPC17xx default to using SYSRESETREQ to reset target

[openocd.git] / tcl / target / lpc17xx.cfg

diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg
index a64783dab2e75edb6119b5552eb7a8dc5785be71..372107f7d4473897aef9f58745382f35f6ae5d3d 100644 (file)
--- a/tcl/target/lpc17xx.cfg
+++ b/tcl/target/lpc17xx.cfg
@@ -49,15 +49,11 @@ if { [info exists CPUROMSIZE] } {
        error "_CPUROMSIZE not set. Please do not include lpc17xx.cfg directly, but the specific chip configuration file (lpc1751.cfg, lpc1764.cfg, etc)."
 }
 
-#delays on reset lines
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
 #jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
 
 # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
@@ -74,6 +70,12 @@ flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
 # we have no idea what clock the target is running at.
 adapter_khz 10
 
+# delays on reset lines
+adapter_nsrst_delay 200
+if {$using_jtag} {
+ jtag_ntrst_delay 200
+}
+
 $_TARGETNAME configure -event reset-init {
        # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
        # "User Flash Mode" where interrupt vectors are _not_ remapped,
@@ -92,6 +94,6 @@ $_TARGETNAME configure -event reset-init {
        mww 0x400FC040 0x01
 }
 
-# if srst is not fitted use VECTRESET to
-# perform a soft reset - SYSRESETREQ is not supported
-cortex_m3 reset_config vectreset
+# if srst is not fitted use SYSRESETREQ to
+# perform a soft reset
+cortex_m reset_config sysresetreq