target/stm32: make APCSW cacheable

[openocd.git] / tcl / target / lpc1850.cfg

diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg
index 1ea7a49e115d559d4371806220c7bd0cc3f68825..925a0498d660750486c923c062ad62b730b03b56 100644 (file)
--- a/tcl/target/lpc1850.cfg
+++ b/tcl/target/lpc1850.cfg
@@ -1,3 +1,4 @@
+source [find target/swj-dp.tcl]
 
 adapter_khz 500
 
@@ -21,11 +22,14 @@ if { [info exists M3_JTAG_TAPID] } {
    set _M3_JTAG_TAPID 0x4ba00477
 }
 
-jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3
 
 set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m3 reset_config sysresetreq
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}