nrf51: Add UICR writing support

[openocd.git] / tcl / target / lpc2148.cfg

diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index d367a8f5750458f2a872d7298fd2d37dd375171b..f3a2011a81e1c91f593c7d4652dc838680562748 100644 (file)
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -1,56 +1,21 @@
-# Use RCLK. If RCLK is not available fall back to 500kHz. 
-# 
-# Depending on cabling you might be able to eek this up to 2000kHz.
-jtag_rclk 500
+# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal
 
-if { [info exists CHIPNAME] } {        
-   set _CHIPNAME $CHIPNAME
-} else {
-   set _CHIPNAME lpc2148
-}
+source [find target/lpc2xxx.cfg]
 
-if { [info exists ENDIAN] } {
-   set _ENDIAN $ENDIAN
-} else {
-   set _ENDIAN little
-}
+# parameters:
+# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
+# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
 
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x4f1f0f0f
+proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
+       # 500kB flash and 32kB SRAM
+       # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
+       setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
 }
 
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate
-# JTAG, power-on reset is not enough, i.e. you need to perform a
-# reset before being able to talk to the LPC2148, attach is not possible.
-
-reset_config trst_and_srst srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
-       # Force target into ARM state.
-       soft_reset_halt
-
-       # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
-       # "User Flash Mode" where interrupt vectors are _not_ remapped,
-       # and reside in flash instead).
-       #
-       # See section 7.1 on page 32 ("Memory Mapping control register") in
-       # "UM10139: Volume 1: LPC214x User Manual", Rev. 02 -- 25 July 2006.
-       # http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2141.lpc2142.lpc2144.lpc2146.lpc2148.pdf
-       mwb 0xE01FC040 0x01
+proc init_targets {} {
+       # default to core clocked with 12MHz crystal
+       echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
+       
+       # setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
+       setup_lpc2148 12000 1500
 }
-
-# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
-flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 calc_checksum