+source [find target/swj-dp.tcl]
adapter_khz 500
set _M4_SWD_TAPID 0x2ba01477
}
+if { [using_jtag] } {
+ set _M4_TAPID $_M4_JTAG_TAPID
+} {
+ set _M4_TAPID $_M4_SWD_TAPID
+}
+
#
# M0 TAP
#
set _M0_JTAG_TAPID 0x0ba01477
}
-jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M4_JTAG_TAPID
+swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
+ -expected-id $_M4_TAPID
+target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
-jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
+if { [using_jtag] } {
+ swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
+ target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
+}
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
-target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
-
-# on this CPU we should use VECTRESET to perform a soft reset and
-# manually reset the periphery
-# SRST or SYSRESETREQ disable the debug interface for the time of
-# the reset and will not fit our requirements for a consistent debug
-# session
-cortex_m reset_config vectreset
+if {![using_hla]} {
+ # on this CPU we should use VECTRESET to perform a soft reset and
+ # manually reset the periphery
+ # SRST or SYSRESETREQ disable the debug interface for the time of
+ # the reset and will not fit our requirements for a consistent debug
+ # session
+ cortex_m reset_config vectreset
+}