jtag: linuxgpiod: drop extra parenthesis

[openocd.git] / tcl / target / nrf52.cfg

diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index c1cbf1a21de711c844d232433f00ef6e6ed5cf4e..0c82c5758a532b24ceade280256babab06421782 100644 (file)
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -1,8 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
 #
 # Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
        set _CHIPNAME $CHIPNAME
@@ -10,6 +13,14 @@ if { [info exists CHIPNAME] } {
        set _CHIPNAME nrf52
 }
 
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x4000
+}
+
 if { [info exists CPUTAPID] } {
        set _CPUTAPID $CPUTAPID
 } else {
@@ -17,12 +28,140 @@ if { [info exists CPUTAPID] } {
 }
 
 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
 
-adapter_khz 10000
+adapter speed 1000
 
-if { ![using_hla] } {
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+if { [using_hla] } {
+       echo ""
+       echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+       echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+       echo "the CTRL-AP so 'nrf52_recover' command will not work."
+       echo "Do not enable UICR APPROTECT."
+       echo ""
+} else {
        cortex_m reset_config sysresetreq
+
+       $_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
+}
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+       set dap [[target current] cget -dap]
+       set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
+       if {$err == 0 && $APPROTECTSTATUS != 1} {
+               echo "****** WARNING ******"
+               echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+               echo "Debug access is denied."
+               echo "Use 'nrf52_recover' to erase and unlock the device."
+               echo ""
+               poll off
+       }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+       set target [target current]
+       set dap [$target cget -dap]
+
+       set IDR [$dap apreg 1 0xfc]
+       if {$IDR != 0x02880000} {
+               echo "Error: Cannot access nRF52 CTRL-AP!"
+               return
+       }
+
+       poll off
+
+       # Reset and trigger ERASEALL task
+       $dap apreg 1 4 0
+       $dap apreg 1 4 1
+
+       for {set i 0} {1} {incr i} {
+               set ERASEALLSTATUS [$dap apreg 1 8]
+               if {$ERASEALLSTATUS == 0} {
+                       echo "$target device has been successfully erased and unlocked."
+                       break
+               }
+               if {$i == 0} {
+                       echo "Waiting for chip erase..."
+               }
+               if {$i >= 150} {
+                       echo "Error: $target recovery failed."
+                       break
+               }
+               sleep 100
+       }
+
+       # Assert reset
+       $dap apreg 1 0 1
+
+       # Deassert reset
+       $dap apreg 1 0 0
+
+       # Reset ERASEALL task
+       $dap apreg 1 4 0
+
+       sleep 100
+       $target arp_examine
+       poll on
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+       targets $_targetname
+
+       # Read FICR.INFO.PART
+       set PART [mrw 0x10000100]
+
+       switch $PART {
+               0x52840 -
+               0x52833 -
+               0x52832 {
+                       if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+                               if { [$_chipname.tpiu cget -port-width] != 4 } {
+                                       echo "Error. Device only supports 4-bit sync traces."
+                                       return
+                               }
+
+                               # Set TRACECONFIG.TRACEMUX to enable synchronous trace
+                               mmw 0x4000055C 0x00020000 0x00010000
+                               $_targetname configure -event reset-end {
+                                       mmw 0x4000055C 0x00020000 0x00010000
+                               }
+                       } else {
+                               # Set TRACECONFIG.TRACEMUX to enable SWO
+                               mmw 0x4000055C 0x00010000 0x00020000
+                               $_targetname configure -event reset-end {
+                                       mmw 0x4000055C 0x00010000 0x00020000
+                               }
+                       }
+               }
+               0x52820 -
+               0x52811 -
+               0x52810 -
+               0x52805 {
+                       echo "Error: Device does not support TPIU"
+                       return
+               }
+               default {
+                       echo "Error: Unknown device"
+                       return
+               }
+       }
 }
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"