openrisc: add support for JTAG Serial Port

[openocd.git] / tcl / target / or1k.cfg

diff --git a/tcl/target/or1k.cfg b/tcl/target/or1k.cfg
index acec70026e84ce3c06d46242381a516d3f0a6fdb..360a0ddf3d80c5f3f4e9e007014a1c084cec769c 100644 (file)
--- a/tcl/target/or1k.cfg
+++ b/tcl/target/or1k.cfg
@@ -61,10 +61,12 @@ if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
 
 # Select the debug unit core we are using. This debug unit as an option.
 
-proc ADBG_USE_HISPEED {}       { return 1 }
+set ADBG_USE_HISPEED           1
+set ENABLE_JSP_SERVER          2
+set ENABLE_JSP_MULTI           4
 
 # If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
 # on burst reads and writes to improve download speeds.
 # This option must match the RTL configured option.
 
-du_select adv [ADBG_USE_HISPEED]
+du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI]