tcl/target/imx6: add yet another SJC tapid

[openocd.git] / tcl / target / pxa255.cfg

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index c79ea4c9a2bc37634f67d18ec2b871e0949f698d..386242597cefd9b3a8ae3d59a455c67170458a62 100644 (file)
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -1,104 +1,59 @@
-if { [info exists CHIPNAME] } {        
-   set  _CHIPNAME $CHIPNAME    
-} else {        
-   set  _CHIPNAME pxa255
+# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
+# This chip is now at end-of-life.  Final orders have been taken.
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME pxa255
 }
 
-if { [info exists ENDIAN] } {  
-   set  _ENDIAN $ENDIAN    
-} else {        
-   set  _ENDIAN little
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
+   set _CPUTAPID 0x69264013
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
-$_TARGETNAME configure -event reset-init {
-       xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
-       #
-       # setup GPIO
-       #
-       mww    0x40E00018  0x00008000  #CPSR0
-       sleep   20
-       mww    0x40E0001C  0x00000002  #GPSR1
-       sleep   20
-       mww    0x40E00020  0x00000008  #GPSR2
-       sleep   20
-       mww    0x40E0000C  0x00008000  #GPDR0
-       sleep   20
-       mww    0x40E00054  0x80000000  #GAFR0_L
-       sleep   20
-       mww    0x40E00058  0x00188010  #GAFR0_H
-       sleep   20
-       mww    0x40E0005C  0x60908018  #GAFR1_L
-       sleep   20
-       mww    0x40E0000C  0x0280E000  #GPDR0
-       sleep   20
-       mww    0x40E00010  0x821C88B2  #GPDR1
-       sleep   20
-       mww    0x40E00014  0x000F03DB  #GPDR2
-       sleep   20
-       mww    0x40E00000  0x000F03DB  #GPLR0
-       sleep   20
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
 
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+       -chain-position $_CHIPNAME.cpu
 
-       mww    0x40F00004  0x00000020  #PSSR
-       sleep   20
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+adapter_khz 300
+$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
 
-       #
-       # setup memory controller
-       #
-       mww    0x48000008  0x01111998  #MSC0
-       sleep   20
-       mww    0x48000010  0x00047ff0  #MSC2
-       sleep   20
-       mww    0x48000014  0x00000000  #MECR
-       sleep   20
-       mww    0x48000028  0x00010504  #MCMEM0
-       sleep   20
-       mww    0x4800002C  0x00010504  #MCMEM1
-       sleep   20
-       mww    0x48000030  0x00010504  #MCATT0
-       sleep   20
-       mww    0x48000034  0x00010504  #MCATT1
-       sleep   20
-       mww    0x48000038  0x00004715  #MCIO0
-       sleep   20
-       mww    0x4800003C  0x00004715  #MCIO1
-       sleep   20
-       #
-       mww    0x48000004  0x03CA4018  #MDREF
-       sleep   20
-       mww    0x48000004  0x004B4018  #MDREF
-       sleep   20
-       mww    0x48000004  0x000B4018  #MDREF
-       sleep   20
-       mww    0x48000004  0x000BC018  #MDREF
-       sleep   20
-       mww    0x48000000  0x00001AC8  #MDCNFG
-       sleep   20
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
 
-       sleep   20
+# reset processing that works with PXA
+proc init_reset {mode} {
+       # assert both resets; equivalent to power-on reset
+       jtag_reset 1 1
 
-       mww    0x48000000  0x00001AC9  #MDCNFG
-       sleep   20
-       mww    0x48000040  0x00000000  #MDMRS
-       sleep   20
-}
-
-reset_config trst_and_srst
+       # drop TRST after at least 32 cycles
+       sleep 1
+       jtag_reset 0 1
 
+       # minimum 32 TCK cycles to wake up the controller
+       runtest 50
 
+       # now the TAP will be responsive; validate scanchain
+       jtag arp_init
 
-#xscale debug_handler 0  0xFFFF0800      # debug handler base address
+       # ... and take it out of reset
+       jtag_reset 0 0
+}
 
+proc jtag_init {} {
+       init_reset startup
+}