target/stm32: make APCSW cacheable

[openocd.git] / tcl / target / samsung_s3c6410.cfg

diff --git a/tcl/target/samsung_s3c6410.cfg b/tcl/target/samsung_s3c6410.cfg
index 91371991d9fa1d0c24da7bbff3a7a5b204e0c4a9..88fe966dcd3b42f7c84963ac6ba0227b6d499da2 100644 (file)
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -7,42 +7,40 @@
 # [and I do not believe it to be accurate, hence the 0xffffffff below]
 
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME s3c6410
+   set _CHIPNAME s3c6410
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
   # this defaults to a bigendian
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
 # trace buffer
-if { [info exists ETBTAPID ] } {
+if { [info exists ETBTAPID] } {
    set _ETBTAPID $ETBTAPID
 } else {
-  # force an error till we get a good number
    set _ETBTAPID 0x2b900f0f
 }
 
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
    set _CPUTAPID 0x07b76f0f
 }
 
 #jtag scan chain
 
 jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID
-jtag newtap $_CHIPNAME cpu     -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm11 -endian $_ENDIAN  -chain-position $_TARGETNAME -variant arm1176
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
-jtag_nsrst_delay 500
+adapter_nsrst_delay 500
 jtag_ntrst_delay 500
 
 #reset configuration