+flash bank $_FLASHNAME stm32f1x 0 $_FLASH_SIZE 0 0 $_TARGETNAME
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+proc stm32f3x_default_reset_start {} {
+ # Reset clock is HSI (8 MHz)
+ adapter speed 1000
+}
+
+proc stm32f3x_default_examine_end {} {
+ # Enable debug during low power modes (uses more power)
+ mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+
+ # Stop watchdog counters during halt
+ mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+}
+
+proc stm32f3x_default_reset_init {} {
+ # Configure PLL to boost clock to HSI x 8 (64 MHz)
+ mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
+ mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
+ mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
+ sleep 10 ;# Wait for PLL to lock
+ mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
+
+ # Boost JTAG frequency
+ adapter speed 8000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
+ targets $_targetname
+
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xe0042004 0x00000020 0
+}