cfg: add stm32 cmsis-dap compliant config
[openocd.git] / tcl / target / stm32f4x.cfg
index 16beaa469d19e48b094d2b9e37cee4196156c388..eafa1226865fe313f5bfb6d88fa7e0341a530ea4 100644 (file)
@@ -1,5 +1,10 @@
 # script for stm32f4x family
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
 } else {
@@ -29,29 +34,39 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 1000
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
   # See STM Document RM0090
-  # Section 32.6.2 - corresponds to Cortex-M4 r0p1
+  # Section 38.6.3 - corresponds to Cortex-M4 r0p1
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
 } else {
   # See STM Document RM0090
-  # Section 32.6.3
-  set _BSTAPID 0x06413041
+  # Section 38.6.2
+  # STM32F405xx/07xx and STM32F415xx/17xx
+  set _BSTAPID1 0x06413041
+  # STM32F42xxx and STM32F43xxx
+  set _BSTAPID2 0x06419041
+}
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+       -expected-id $_BSTAPID2
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
@@ -60,4 +75,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq

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