tcl/target/stm32f4x: add F401 and F411 IDs

[openocd.git] / tcl / target / stm32f4x.cfg

diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index 30ec686ca0924986dc56a91aa63d8dada41e9e0c..ecd39de77ca5e82070364738007d4c26b7fb75bb 100644 (file)
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -29,9 +29,13 @@ if { [info exists WORKAREASIZE] } {
 if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # See STM Document RM0090
-  # Section 38.6.3 - corresponds to Cortex-M4 r0p1
-   set _CPUTAPID 0x4ba00477
+   if { [using_jtag] } {
+      # See STM Document RM0090
+      # Section 38.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -45,11 +49,20 @@ if { [info exists BSTAPID] } {
   set _BSTAPID1 0x06413041
   # STM32F42xxx and STM32F43xxx
   set _BSTAPID2 0x06419041
+  # See STM Document RM0368 (Rev. 3)
+  # STM32F401B/C
+  set _BSTAPID3 0x06423041
+  # STM32F401D/E
+  set _BSTAPID4 0x06433041
+  # See STM Document RM0383 (Rev 2)
+  # STM32F411
+  set _BSTAPID5 0x06431041
 }
 
 if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
-       -expected-id $_BSTAPID2
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
+     -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+     -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
@@ -73,6 +86,8 @@ if {[using_jtag]} {
  jtag_ntrst_delay 100
 }
 
-# if srst is not fitted use SYSRESETREQ to
-# perform a soft reset
-cortex_m reset_config sysresetreq
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}