nrf51: Add UICR writing support

[openocd.git] / tcl / target / stm32l.cfg

diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg
index 5c3d3686f4ad6a7ac60160263ed6219dfd06b7bc..f9f7425b9a7bb9925a21b9921710e908220b176e 100644 (file)
--- a/tcl/target/stm32l.cfg
+++ b/tcl/target/stm32l.cfg
@@ -1,23 +1,28 @@
 # script for stm32l
 
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+
 if { [info exists CHIPNAME] } {
-   set  _CHIPNAME $CHIPNAME
+   set _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME stm32l
+   set _CHIPNAME stm32l
 }
 
 if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
+   set _ENDIAN $ENDIAN
 } else {
-   set  _ENDIAN little
+   set _ENDIAN little
 }
 
 # Work-area is a space in RAM used for flash programming
-# By default use 14kB
+# By default use 10kB
 if { [info exists WORKAREASIZE] } {
-   set  _WORKAREASIZE $WORKAREASIZE
+   set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set  _WORKAREASIZE 0x3800
+   set _WORKAREASIZE 0x2800
 }
 
 # JTAG speed should be <= F_CPU/6.
@@ -25,19 +30,22 @@ if { [info exists WORKAREASIZE] } {
 adapter_khz 100
 
 adapter_nsrst_delay 100
-jtag_ntrst_delay 100
+if {$using_jtag} {
+ jtag_ntrst_delay 100
+}
 
 #jtag scan chain
-if { [info exists CPUTAPID ] } {
+if { [info exists CPUTAPID] } {
    set _CPUTAPID $CPUTAPID
 } else {
   # See STM Document RM0038
   # Section 24.6.3
    set _CPUTAPID 0x4ba00477
 }
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-if { [info exists BSTAPID ] } {
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
    # FIXME this never gets used to override defaults...
    set _BSTAPID $BSTAPID
 } else {
@@ -45,21 +53,23 @@ if { [info exists BSTAPID ] } {
   # Section 24.6.2
   set _BSTAPID 0x06416041
 }
-jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+
+if {$using_jtag} {
+ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
+}
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-
 # flash size will be probed
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
 
 # if srst is not fitted use SYSRESETREQ to
 # perform a soft reset
-cortex_m3 reset_config sysresetreq
+cortex_m reset_config sysresetreq
 
 proc stm32l_enable_HSI {} {
        # Enable HSI as clock source