stm32l: split l0/l1 support no jtag, different HSI settings

[openocd.git] / tcl / target / stm32l1.cfg

diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
new file mode 100644 (file)
index 0000000..8b83d3f
--- /dev/null
+++ b/tcl/target/stm32l1.cfg
@@ -0,0 +1,108 @@
+#
+# stm32l1 devices support both JTAG and SWD transports.
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 10kB
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2800
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
+adapter_khz 300
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0038
+      # Section 30.6.3 - corresponds to Cortex-M3 r2p0
+      set _CPUTAPID 0x4ba00477
+   } else {
+      # SWD IDCODE (single drop, arm)
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   # FIXME this never gets used to override defaults...
+   set _BSTAPID $BSTAPID
+} else {
+   # See STM Document RM0038 Section 30.6.1
+   # (section 30.6.2 seems incorrect, at least in RM0038 DocID 15965 Rev 10)
+
+   # Low and medium density
+   set _BSTAPID1 0x06416041
+   # Cat.3 device (medium+ density)
+   set _BSTAPID2 0x06427041
+   # Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
+   set _BSTAPID3 0x06436041
+   # Cat.5 device (high density), STM32L15/6xxE
+   set _BSTAPID4 0x06437041
+}
+
+if {[using_jtag]} {
+   swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l_enable_HSI {} {
+       # Enable HSI as clock source
+       echo "STM32L: Enabling HSI"
+
+       # Set HSION in RCC_CR
+       mww 0x40023800 0x00000101
+
+       # Set HSI as SYSCLK
+       mww 0x40023808 0x00000001
+
+       # Increase JTAG speed
+       adapter_khz 2000
+}
+
+$_TARGETNAME configure -event reset-init {
+       stm32l_enable_HSI
+}
+
+$_TARGETNAME configure -event reset-start {
+       adapter_khz 300
+}