#
source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
# FIXME this never gets used to override defaults...
set _BSTAPID $BSTAPID
} else {
- # See STM Document RM0038 Section 30.6.1
- # (section 30.6.2 seems incorrect, at least in RM0038 DocID 15965 Rev 10)
+ # See STM Document RM0038 Section 30.6.1 Rev. 12
# Low and medium density
set _BSTAPID1 0x06416041
+ # Cat.2 device (medium+ density)
+ set _BSTAPID2 0x06429041
# Cat.3 device (medium+ density)
- set _BSTAPID2 0x06427041
+ set _BSTAPID3 0x06427041
# Cat.4 device, STM32L15/6xxD or Cat.3 device, some STM32L15/6xxC-A models
- set _BSTAPID3 0x06436041
+ set _BSTAPID4 0x06436041
# Cat.5 device (high density), STM32L15/6xxE
- set _BSTAPID4 0x06437041
+ set _BSTAPID5 0x06437041
}
if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
+ swj_newdap $_CHIPNAME bs -irlen 5 \
+ -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
+ -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
}
set _TARGETNAME $_CHIPNAME.cpu
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+reset_config srst_nogate
+
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
$_TARGETNAME configure -event reset-start {
adapter_khz 300
}
+
+$_TARGETNAME configure -event examine-end {
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000007 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+ mww 0xE0042008 0x00001800
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0042004 0x00000020 0
+}