flash Kinetis: Detect RESET/WDOG loop, fix detection of secured MCU

[openocd.git] / tcl / target / stm32l1.cfg

diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index 13487c4e289cea7a55e140893988d98ccfea5824..790c495b3585ec368063daafe5e1bd251a809d0a 100644 (file)
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -3,6 +3,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -65,7 +66,7 @@ if { [info exists BSTAPID] } {
 
 if {[using_jtag]} {
    swj_newdap $_CHIPNAME bs -irlen 5 \
-   -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 expected-id $_BSTAPID3 \
+   -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
    -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
 }
 
@@ -107,3 +108,19 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -event reset-start {
        adapter_khz 300
 }
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xE0042004 0x00000020 0
+}