stm32l4: Add cpu and stm32l4discovery board configuration.

[openocd.git] / tcl / target / stm32l4x.cfg

diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
new file mode 100644 (file)
index 0000000..8b827ad
--- /dev/null
+++ b/tcl/target/stm32l4x.cfg
@@ -0,0 +1,106 @@
+# script for stm32l4x family
+
+#
+# stm32l4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 64kB ram, use 32kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0351
+      # Section 44.6.3 - corresponds to Cortex-M4 r0p1
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0351
+  # Section 44.6.3
+  # STM32L4X6
+  set _BSTAPID1 0x06415041
+}
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz
+#
+# Since we may be running of an RC oscilator, we crank down the speed a
+# bit more to be on the safe side. Perhaps superstition, but if are
+# running off a crystal, we can run closer to the limit. Note
+# that there can be a pretty wide band where things are more or less stable.
+adapter_khz 500
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+       # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
+       # Configure system to use MSI 24 MHz clock, compliant with VOS default (2).
+       # 3 WS compliant with VOS=2 and 24 MHz.
+       mww 0x40022000 0x00000102   ;# FLASH_ACR = PRFTBE | 3(Latency)
+       mww 0x4002100C 0x00000099   ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
+       # Boost JTAG frequency
+       adapter_khz 4000
+}
+
+$_TARGETNAME configure -event examine-end {
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+       # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+       # change this value accordingly to configure trace pins
+       # assignment
+       mmw 0xE0042004 0x00000020 0
+}