tcl/stm32mp15x: freeze watchdog, recover SWD after power cycle

[openocd.git] / tcl / target / stm32mp15x.cfg

diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
index e50ef9c20ec70373b165f48e529b41022c9822d0..639fbabe06e9dc23a0b56cf70a174024e513724c 100644 (file)
--- a/tcl/target/stm32mp15x.cfg
+++ b/tcl/target/stm32mp15x.cfg
@@ -97,6 +97,9 @@ axi_secure
 proc dbgmcu_enable_debug {} {
        # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
        catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+       # freeze watchdog 1 and 2 on cores halted
+       catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
+       catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
 proc toggle_cpu0_dbg_claim0 {} {
@@ -116,7 +119,7 @@ proc rcc_enable_traceclk {} {
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
 $_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
 $_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
 $_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}