Ensure that DaVinci chips can't start with a too-fast JTAG clock.

[openocd.git] / tcl / target / ti_dm365.cfg

diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 4f22ea27dd05b05d672dd7433872e6c15b43cd7e..06a52d28f58b714c21aebf63887ea472b368944a 100644 (file)
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -88,6 +88,12 @@ $_TARGETNAME configure \
        -work-area-size 0x4000 \
        -work-area-backup 0
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable