tcl/target/ti_k3: Rename m4 target as general purpose mcu

[openocd.git] / tcl / target / ti_k3.cfg

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 8fb71482c9e9160b6ca5a348ce90c1f447ddeba2..e397d2255cae037cfdc5a1d708d29dfbcbd7cb00 100644 (file)
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -27,11 +27,11 @@ if { [info exists V8_SMP_DEBUG] } {
 
 # Common Definitions
 
-# CM3 the very first processor - all current SoCs have it.
+# System Controller is the very first processor - all current SoCs have it.
 set CM3_CTIBASE                {0x3C016000}
 
-# M3 power-ap unlock offsets
-set _m3_ap_unlock_offsets {0xf0 0x44}
+# sysctrl power-ap unlock offsets
+set _sysctrl_ap_unlock_offsets {0xf0 0x44}
 
 # All the ARMV8s are the next processors.
 #                 CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
@@ -43,13 +43,13 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 
-# Finally an M4F
+# Finally an General Purpose(GP) MCU
 set CM4_CTIBASE                {0x20001000}
 
-# M4 may be present on some very few SoCs
-set _mcu_m4_cores 0
-# M4 power-ap unlock offsets
-set _m4_ap_unlock_offsets {0xf0 0x60}
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
 
 # Set configuration overrides for each SOC
 switch $_soc {
@@ -70,8 +70,8 @@ switch $_soc {
                set _main1_r5_cores 0
                set _main1_base_core_id 0
 
-               # M3 power-ap unlock offsets
-               set _m3_ap_unlock_offsets {0xf0 0x50}
+               # Sysctrl power-ap unlock offsets
+               set _sysctrl_ap_unlock_offsets {0xf0 0x50}
        }
        am642 {
                set _CHIPNAME am642
@@ -95,7 +95,7 @@ switch $_soc {
                set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
 
                # M4 processor
-               set _mcu_m4_cores 1
+               set _gp_mcu_cores 1
        }
        j721e {
                set _CHIPNAME j721e
@@ -147,22 +147,22 @@ set _TARGETNAME $_CHIPNAME.cpu
 
 set _CTINAME $_CHIPNAME.cti
 
-# M3 is always present
-cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
-$_TARGETNAME.m3 configure -event reset-assert { }
+# sysctrl is always present
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+$_TARGETNAME.sysctrl configure -event reset-assert { }
 
-proc m3_up {} {
-       # To access M3, we need to enable the JTAG access for the same.
+proc sysctrl_up {} {
+       # To access sysctrl, we need to enable the JTAG access for the same.
        # Ensure Power-AP unlocked
-       $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
-       $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 1] 0x00102098
+       $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
+       $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
 
-       $::_TARGETNAME.m3 arp_examine
+       $::_TARGETNAME.sysctrl arp_examine
 }
 
-$_TARGETNAME.m3 configure -event gdb-attach {
-       m3_up
+$_TARGETNAME.sysctrl configure -event gdb-attach {
+       sysctrl_up
        # gdb-attach default rule
        halt 1000
 }
@@ -246,22 +246,22 @@ if { $_main1_r5_cores != 0 } {
        }
 }
 
-if { $_mcu_m4_cores != 0 } {
-       cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
-       target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
-       $_TARGETNAME.m4 configure -event reset-assert { }
+if { $_gp_mcu_cores != 0 } {
+       cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+       target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+       $_TARGETNAME.gp_mcu configure -event reset-assert { }
 
-       proc m4_up {} {
-               # To access M4, we need to enable the JTAG access for the same.
+       proc gp_mcu_up {} {
+               # To access GP MCU, we need to enable the JTAG access for the same.
                # Ensure Power-AP unlocked
-               $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
-               $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
+               $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+               $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
 
-               $::_TARGETNAME.m4 arp_examine
+               $::_TARGETNAME.gp_mcu arp_examine
        }
 
-       $_TARGETNAME.m4 configure -event gdb-attach {
-               m4_up
+       $_TARGETNAME.gp_mcu configure -event gdb-attach {
+               gp_mcu_up
                # gdb-attach default rule
                halt 1000
        }