X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=NEWS;h=498797b1f4855cd5732f8789330890c487179155;hp=b7eb0f0f4ad8c19fab9c149692afe74e171227c5;hb=747d6f22868dd87cb54341cc22d9eb3687039735;hpb=5782999f6030acb560a3b02da10354eb099c45a4

diff --git a/NEWS b/NEWS
index b7eb0f0f4a..498797b1f4 100644
--- a/NEWS
+++ b/NEWS
@@ -15,16 +15,21 @@ Target Layer:
 		- recognize TrustZone "Secure Monitor" mode
 		- "arm regs" command output changed
 		- register names use "sp" not "r13"
+		- add top-level "mcr" and "mrc" commands, replacing
+		  various core-specific operations
+		- basic semihosting support
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
 		- accelerated GDB memory checksum
 		- support "arm regs" command
 		- can access all core modes and registers
+		- watchpoint support
 	Cortex-A8
 		- support "arm regs" command
 		- can access all core modes and registers
 		- supports "reset-assert" event (used on OMAP3530)
+		- watchpoint support
 	Cortex-M3
 		- Exposed DWT registers like cycle counter