X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=431f11cb2be4a00f07c7d78f45d1a172a23abcd6;hp=7f5b72e0790806580f18785fbd67fcf9f062e1a5;hb=867bdb2e9248a974f7db0a99fbe5d2dd8b46d25d;hpb=22ad1c0f6057aed642d5b1229b24e52dd26b1ec4

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7f5b72e079..431f11cb2b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4913,16 +4913,13 @@ functionality is available through the @command{flash write_bank},
 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
 @var{USER1} instruction.
-@item @var{dr_length} ... is the length of the DR register. This will be 1 for
-@file{xilinx_bscan_spi.py} bitstreams and most other cases.
 @end itemize
 
 @example
 target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
 set _XILINX_USER1 0x02
-set _DR_LENGTH 1
 flash bank $_FLASHNAME spi 0x0 0 0 0 \
-           $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH
+           $_TARGETNAME $_XILINX_USER1
 @end example
 @end deffn