X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=676099429d26b2b49da2c86f4e32420faac32f0c;hp=de73bec71283630afccba088f960b47eb512be24;hb=75cdc8a260e081752698f374d4cd6e97e84eb6cb;hpb=e996452089fd5ffba34094958e87d51c1fcf8619

diff --git a/doc/openocd.texi b/doc/openocd.texi
index de73bec712..676099429d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5114,14 +5114,23 @@ ETM support in OpenOCD doesn't seem to be widely used yet.
 @quotation Issues
 ETM support may be buggy, and at least some @command{etm config}
 parameters should be detected by asking the ETM for them.
+
+ETM trigger events could also implement a kind of complex
+hardware breakpoint, much more powerful than the simple
+watchpoint hardware exported by EmbeddedICE modules.
+@emph{Such breakpoints can be triggered even when using the
+dummy trace port driver}.
+
 It seems like a GDB hookup should be possible,
-as well as triggering trace on specific events
+as well as tracing only during specific states
 (perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
+
 There should be GUI tools to manipulate saved trace data and help
 analyse it in conjunction with the source code.
 It's unclear how much of a common interface is shared
 with the current XScale trace support, or should be
 shared with eventual Nexus-style trace module support.
+
 At this writing (September 2009) only ARM7 and ARM9 support
 for ETM modules is available.  The code should be able to
 work with some newer cores; but not all of them support
@@ -5135,7 +5144,10 @@ ETM setup is coupled with the trace port driver configuration.
 Declares the ETM associated with @var{target}, and associates it
 with a given trace port @var{driver}.  @xref{Trace Port Drivers}.
 
-Several of the parameters must reflect the trace port configuration.
+Several of the parameters must reflect the trace port capabilities,
+which are a function of silicon capabilties (exposed later
+using @command{etm info}) and of what hardware is connected to
+that port (such as an external pod, or ETB).
 The @var{width} must be either 4, 8, or 16.
 The @var{mode} must be @option{normal}, @option{multiplexted},
 or @option{demultiplexted}.
@@ -5151,6 +5163,9 @@ what CPU activities are traced.
 
 @deffn Command {etm info}
 Displays information about the current target's ETM.
+This includes resource counts from the @code{ETM_CONFIG} register,
+as well as silicon capabilities (except on rather old modules).
+from the @code{ETM_SYS_CONFIG} register.
 @end deffn
 
 @deffn Command {etm status}
@@ -5431,23 +5446,6 @@ Display cp15 register @var{regnum};
 else if a @var{value} is provided, that value is written to that register.
 @end deffn
 
-@deffn Command {arm720t mdw_phys} addr [count]
-@deffnx Command {arm720t mdh_phys} addr [count]
-@deffnx Command {arm720t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm720t mww_phys} addr word
-@deffnx Command {arm720t mwh_phys} addr halfword
-@deffnx Command {arm720t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @subsection ARM9 specific commands
 @cindex ARM9
 
@@ -5462,6 +5460,8 @@ ARMv5TE architecture instead of ARMv4T.
 
 @c 9-june-2009:  tried this on arm920t, it didn't work.
 @c no-params always lists nothing caught, and that's how it acts.
+@c 23-oct-2009:  doesn't work _consistently_ ... as if the ICE
+@c versions have different rules about when they commit writes.
 
 @anchor{arm9tdmi vector_catch}
 @deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
@@ -5478,7 +5478,7 @@ vector catch hardware to intercept
 @option{all} of the hardware vectors,
 @option{none} of them,
 or a list with one or more of the following:
-@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
+@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
 @option{irq} @option{fiq}.
 @end deffn
 
@@ -5508,23 +5508,6 @@ Else if that value is written using the specified @var{address},
 or using zero if no other address is not provided.
 @end deffn
 
-@deffn Command {arm920t mdw_phys} addr [count]
-@deffnx Command {arm920t mdh_phys} addr [count]
-@deffnx Command {arm920t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm920t mww_phys} addr word
-@deffnx Command {arm920t mwh_phys} addr halfword
-@deffnx Command {arm920t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @deffn Command {arm920t read_cache} filename
 Dump the content of ICache and DCache to a file named @file{filename}.
 @end deffn
@@ -5556,23 +5539,6 @@ If a @var{value} is provided, that value is written to that register.
 Else that register is read and displayed.
 @end deffn
 
-@deffn Command {arm926ejs mdw_phys} addr [count]
-@deffnx Command {arm926ejs mdh_phys} addr [count]
-@deffnx Command {arm926ejs mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm926ejs mww_phys} addr word
-@deffnx Command {arm926ejs mwh_phys} addr halfword
-@deffnx Command {arm926ejs mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
 @subsection ARM966E specific commands
 @cindex ARM966E