X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=9f3a8515c94ff884e63c2d329f717202e9d4eade;hp=5a8648b1c905a6812b79a602454d4fc09ce1f4e1;hb=2467da4b4aad750d2b3d56998bcf07674047687a;hpb=76afadeb7b4e428c1543b4f5218aa253bdd85e40;ds=sidebyside diff --git a/doc/openocd.texi b/doc/openocd.texi index 5a8648b1c9..9f3a8515c9 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -72,6 +72,7 @@ Free Documentation License''. * TAP Declaration:: TAP Declaration * CPU Configuration:: CPU Configuration * Flash Commands:: Flash Commands +* Flash Programming:: Flash Programming * NAND Flash Commands:: NAND Flash Commands * PLD/FPGA Commands:: PLD/FPGA Commands * General Commands:: General Commands @@ -155,13 +156,13 @@ OpenOCD internally. @xref{Debug Adapter Hardware}. @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T, ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and -Cortex-M3 (Stellaris LM3 and ST STM32) based cores to be +Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be debugged via the GDB protocol. @b{Flash Programing:} Flash writing is supported for external CFI compatible NOR flashes (Intel and AMD/Spansion command set) and several -internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and -STM32x). Preliminary support for various NAND flash controllers +internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, +STM32x and EFM32). Preliminary support for various NAND flash controllers (LPC3180, Orion, S3C24xx, more) controller is included. @section OpenOCD Web Site @@ -4596,6 +4597,7 @@ but most don't bother. @cindex flash reading @cindex flash writing @cindex flash programming +@anchor{Flash Programming Commands} One feature distinguishing NOR flash from NAND or serial flash technologies is that for read access, it acts exactly like any other addressible memory. @@ -4739,6 +4741,13 @@ specifies "to the end of the flash bank". The @var{num} parameter is a value shown by @command{flash banks}. @end deffn +@anchor{program} +@deffn Command {program} filename [verify] [reset] [offset] +This is a helper script that simplifies using OpenOCD as a standalone +programmer. The only required parameter is @option{filename}, the others are optional. +@xref{Flash Programming}. +@end deffn + @anchor{Flash Driver List} @section Flash Driver List As noted above, the @command{flash bank} command requires a driver name, @@ -4980,6 +4989,18 @@ The AVR 8-bit microcontrollers from Atmel integrate flash memory. @comment - defines mass_erase ... pointless given flash_erase_address @end deffn +@deffn {Flash Driver} efm32 +All members of the EFM32 microcontroller family from Energy Micro include +internal flash and use ARM Cortex M3 cores. The driver automatically recognizes +a number of these chips using the chip identification register, and +autoconfigures itself. +@example +flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME +@end example +@emph{The current implementation is incomplete. Unprotecting flash pages is not +supported.} +@end deffn + @deffn {Flash Driver} lpc2000 Most members of the LPC1700 and LPC2000 microcontroller families from NXP include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores. @@ -5204,7 +5225,6 @@ standard @command{flash erase_address} command.} @example flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME @end example -@end deffn @deffn Command {stellaris recover bank_id} Performs the @emph{Recovering a "Locked" Device} procedure to @@ -5220,10 +5240,11 @@ if more than one Stellaris chip is connected, the procedure is applied to all of them. @end quotation @end deffn +@end deffn @deffn {Flash Driver} stm32f1x -All members of the STM32f1x microcontroller family from ST Microelectronics -include internal flash and use ARM Cortex M3 cores. +All members of the STM32F0, STM32F1 and STM32F3 microcontroller families +from ST Microelectronics include internal flash and use ARM Cortex-M0/M3/M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. @@ -5231,6 +5252,14 @@ the chip identification register, and autoconfigures itself. flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME @end example +Note that some devices have been found that have a flash size register that contains +an invalid value, to workaround this issue you can override the probed value used by +the flash driver. + +@example +flash bank $_FLASHNAME stm32f1x 0 0x20000 0 0 $_TARGETNAME +@end example + If you have a target with dual flash banks then define the second bank as per the following example. @example @@ -5266,10 +5295,45 @@ The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @deffn {Flash Driver} stm32f2x -All members of the STM32f2x microcontroller family from ST Microelectronics -include internal flash and use ARM Cortex M3 cores. +All members of the STM32F2 and STM32F4 microcontroller families from ST Microelectronics +include internal flash and use ARM Cortex-M3/M4 cores. The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself. + +Note that some devices have been found that have a flash size register that contains +an invalid value, to workaround this issue you can override the probed value used by +the flash driver. + +@example +flash bank $_FLASHNAME stm32f2x 0 0x20000 0 0 $_TARGETNAME +@end example + +Some stm32f2x-specific commands are defined: + +@deffn Command {stm32f2x lock} num +Locks the entire stm32 device. +The @var{num} parameter is a value shown by @command{flash banks}. +@end deffn + +@deffn Command {stm32f2x unlock} num +Unlocks the entire stm32 device. +The @var{num} parameter is a value shown by @command{flash banks}. +@end deffn +@end deffn + +@deffn {Flash Driver} stm32lx +All members of the STM32L microcontroller families from ST Microelectronics +include internal flash and use ARM Cortex-M3 cores. +The driver automatically recognizes a number of these chips using +the chip identification register, and autoconfigures itself. + +Note that some devices have been found that have a flash size register that contains +an invalid value, to workaround this issue you can override the probed value used by +the flash driver. + +@example +flash bank $_FLASHNAME stm32lx 0 0x20000 0 0 $_TARGETNAME +@end example @end deffn @deffn {Flash Driver} str7x @@ -5525,6 +5589,38 @@ Write the binary file @var{filename} to mflash bank @var{num}, starting at @var{offset} bytes from the beginning of the bank. @end deffn +@node Flash Programming +@chapter Flash Programming + +OpenOCD implements numerous ways to program the target flash, whether internal or external. +Programming can be acheived by either using GDB @ref{Programming using GDB}, or using the cmds given in @ref{Flash Programming Commands}. + +@*To simplify using the flash cmds directly a jimtcl script is available that handles the programming and verify stage. +OpenOCD will program/verify/reset the target and shutdown. + +The script is executed as follows and by default the following actions will be peformed. +@enumerate +@item 'init' is executed. +@item 'reset init' is called to reset and halt the target, any 'reset init' scripts are executed. +@item @code{flash write_image} is called to erase and write any flash using the filename given. +@item @code{verify_image} is called if @option{verify} parameter is given. +@item @code{reset run} is called if @option{reset} parameter is given. +@item OpenOCD is shutdown. +@end enumerate + +An example of usage is given below. @xref{program}. + +@example +# program and verify using elf/hex/s19. verify and reset +# are optional parameters +openocd -f board/stm32f3discovery.cfg \ + -c "program filename.elf verify reset" + +# binary files need the flash address passing +openocd -f board/stm32f3discovery.cfg \ + -c "program filename.bin 0x08000000" +@end example + @node NAND Flash Commands @chapter NAND Flash Commands @cindex NAND @@ -7816,6 +7912,7 @@ using @command{gdb -x filename}. @section Programming using GDB @cindex Programming using GDB +@anchor{Programming using GDB} By default the target memory map is sent to GDB. This can be disabled by the following OpenOCD configuration option: