X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=doc%2Fopenocd.texi;h=a60474ba1bdadab54c6dcd18ae65e18976d41dd8;hp=497a20b5b138a79cf1315fc211347285046c6e0f;hb=45f0e6d0626e4541158198c271519175ae79f5b5;hpb=29964c79846ea419e113dc90c0d74f1a7e16e70a;ds=sidebyside diff --git a/doc/openocd.texi b/doc/openocd.texi index 497a20b5b1..a60474ba1b 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -2408,11 +2408,10 @@ This driver is for adapters using the MPSSE (Multi-Protocol Synchronous Serial Engine) mode built into many FTDI chips, such as the FT2232, FT4232 and FT232H. The driver is using libusb-1.0 in asynchronous mode to talk to the FTDI device, -bypassing intermediate libraries like libftdi of D2XX. +bypassing intermediate libraries like libftdi or D2XX. -A major improvement of this driver is that support for new FTDI based adapters -can be added competely through configuration files, without the need to patch -and rebuild OpenOCD. +Support for new FTDI based adapters can be added competely through +configuration files, without the need to patch and rebuild OpenOCD. The driver uses a signal abstraction to enable Tcl configuration files to define outputs for one or several FTDI GPIO. These outputs can then be @@ -2421,6 +2420,12 @@ are reserved for nTRST, nSRST and LED (for blink) so that they, if defined, will be used for their customary purpose. Inputs can be read using the @command{ftdi_get_signal} command. +To support SWD, a signal named SWD_EN must be defined. It is set to 1 when the +SWD protocol is selected. When set, the adapter should route the SWDIO pin to +the data input. An SWDIO_OE signal, if defined, will be set to 1 or 0 as +required by the protocol, to tell the adapter to drive the data output onto +the SWDIO pin or keep the SWDIO pin Hi-Z, respectively. + Depending on the type of buffer attached to the FTDI GPIO, the outputs have to be controlled differently. In order to support tristateable signals such as nSRST, both a data GPIO and an output-enable GPIO can be specified for each @@ -2439,9 +2444,8 @@ These interfaces have several commands, used to configure the driver before initializing the JTAG scan chain: @deffn {Config Command} {ftdi_vid_pid} [vid pid]+ -The vendor ID and product ID of the adapter. If not specified, the FTDI -default values are used. -Currently, up to eight [@var{vid}, @var{pid}] pairs may be given, e.g. +The vendor ID and product ID of the adapter. Up to eight +[@var{vid}, @var{pid}] pairs may be given, e.g. @example ftdi_vid_pid 0x0403 0xcff8 0x15ba 0x0003 @end example @@ -2702,6 +2706,26 @@ Reset the current configuration. @deffn {Command} {jlink config write} Write the current configuration to the internal persistent storage. @end deffn +@deffn {Command} {jlink emucom write } +Write data to an EMUCOM channel. The data needs to be encoded as hexadecimal +pairs. + +The following example shows how to write the three bytes 0xaa, 0x0b and 0x23 to +the EMUCOM channel 0x10: +@example +> jlink emucom write 0x10 aa0b23 +@end example +@end deffn +@deffn {Command} {jlink emucom read } +Read data from an EMUCOM channel. The read data is encoded as hexadecimal +pairs. + +The following example shows how to read 4 bytes from the EMUCOM channel 0x0: +@example +> jlink emucom read 0x0 4 +77a90000 +@end example +@end deffn @deffn {Config} {jlink usb} <@option{0} to @option{3}> Set the USB address of the interface, in case more than one adapter is connected to the host. If not specified, USB addresses are not considered. Device @@ -2912,6 +2936,27 @@ pinout. @end deffn +@deffn {Interface Driver} {openjtag} +OpenJTAG compatible USB adapter. +This defines some driver-specific commands: + +@deffn {Config Command} {openjtag_variant} variant +Specifies the variant of the OpenJTAG adapter (see @uref{http://www.openjtag.org/}). +Currently valid @var{variant} values include: + +@itemize @minus +@item @b{standard} Standard variant (default). +@item @b{cy7c65215} Cypress CY7C65215 Dual Channel USB-Serial Bridge Controller +(see @uref{http://www.cypress.com/?rID=82870}). +@end itemize +@end deffn + +@deffn {Config Command} {openjtag_device_desc} string +The USB device description string of the adapter. +This value is only used with the standard variant. +@end deffn +@end deffn + @section Transport Configuration @cindex Transport As noted earlier, depending on the version of OpenOCD you use, @@ -3959,6 +4004,7 @@ At this writing, the supported CPU types are: @item @code{cortex_a} -- this is an ARMv7 core with an MMU @item @code{cortex_m} -- this is an ARMv7 core, supporting only the compact Thumb2 instruction set. +@item @code{aarch64} -- this is an ARMv8-A core with an MMU @item @code{dragonite} -- resembles arm966e @item @code{dsp563xx} -- implements Freescale's 24-bit DSP. (Support for this is still incomplete.) @@ -3991,7 +4037,7 @@ The CPU name used by OpenOCD will reflect the CPU design that was licenced, not a vendor brand which incorporates that design. Name prefixes like arm7, arm9, arm11, and cortex reflect design generations; -while names like ARMv4, ARMv5, ARMv6, and ARMv7 +while names like ARMv4, ARMv5, ARMv6, ARMv7 and ARMv8 reflect an architecture version implemented by a CPU design. @anchor{targetconfiguration} @@ -4122,14 +4168,23 @@ The value should normally correspond to a static mapping for the @anchor{rtostype} @item @code{-rtos} @var{rtos_type} -- enable rtos support for target, -@var{rtos_type} can be one of @option{auto}|@option{eCos}|@option{ThreadX}| -@option{FreeRTOS}|@option{linux}|@option{ChibiOS}|@option{embKernel}|@option{mqx} +@var{rtos_type} can be one of @option{auto}, @option{eCos}, +@option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS}, +@option{embKernel}, @option{mqx}, @option{uCOS-III} @xref{gdbrtossupport,,RTOS Support}. @item @code{-defer-examine} -- skip target examination at initial JTAG chain scan and after a reset. A manual call to arp_examine is required to access the target for debugging. +@item @code{-ap-num} @var{ap_number} -- set DAP access port for target, +@var{ap_number} is the numeric index of the DAP AP the target is connected to. +Use this option with systems where multiple, independent cores are connected +to separate access ports of the same DAP. + +@item @code{-ctibase} @var{address} -- set base address of Cross-Trigger interface (CTI) connected +to the target. Currently, only the @code{aarch64} target makes use of this option, where it is +a mandatory configuration for the target run control. @end itemize @end deffn @@ -4601,9 +4656,10 @@ and write the contents to the binary @file{filename}. The @var{num} parameter is a value shown by @command{flash banks}. @end deffn -@deffn Command {flash verify_bank} num filename offset +@deffn Command {flash verify_bank} num filename [offset] Compare the contents of the binary file @var{filename} with the contents of the -flash @var{num} starting at @var{offset}. Fails if the contents do not match. +flash bank @var{num} starting at @var{offset}. If @var{offset} is omitted, +start at the beginning of the flash bank. Fail if the contents do not match. The @var{num} parameter is a value shown by @command{flash banks}. @end deffn @@ -4664,12 +4720,15 @@ and possibly stale information. @anchor{flashprotect} @deffn Command {flash protect} num first last (@option{on}|@option{off}) -Enable (@option{on}) or disable (@option{off}) protection of flash sectors -in flash bank @var{num}, starting at sector @var{first} +Enable (@option{on}) or disable (@option{off}) protection of flash blocks +in flash bank @var{num}, starting at protection block @var{first} and continuing up to and including @var{last}. -Providing a @var{last} sector of @option{last} +Providing a @var{last} block of @option{last} specifies "to the end of the flash bank". The @var{num} parameter is a value shown by @command{flash banks}. +The protection block is usually identical to a flash sector. +Some devices may utilize a protection block distinct from flash sector. +See @command{flash info} for a list of protection blocks. @end deffn @deffn Command {flash padded_value} num value @@ -4706,8 +4765,10 @@ the flash bank defined at address 0x1fc00000. Any cmds executed on the virtual banks are actually performed on the physical banks. @example flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME -flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME -flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME +flash bank vbank0 virtual 0xbfc00000 0 0 0 \ + $_TARGETNAME $_FLASHNAME +flash bank vbank1 virtual 0x9fc00000 0 0 0 \ + $_TARGETNAME $_FLASHNAME @end example @end deffn @@ -4773,8 +4834,8 @@ Since signaling between JTAG and SPI is compatible, all that is required for a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate the flash chip select when the JTAG state machine is in SHIFT-DR. Such a bitstream for several Xilinx FPGAs can be found in -@file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires migen -(@url{http://github.com/m-labs/migen}) and a Xilinx toolchain to build. +@file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires +@uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build. This flash bank driver requires a target on a JTAG tap and will access that tap directly. Since no support from the target is needed, the target can be a @@ -4797,7 +4858,8 @@ For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga set _XILINX_USER1 0x02 set _DR_LENGTH 1 -flash bank $_FLASHNAME spi 0x0 0 0 0 $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH +flash bank $_FLASHNAME spi 0x0 0 0 0 \ + $_TARGETNAME $_XILINX_USER1 $_DR_LENGTH @end example @end deffn @@ -4903,7 +4965,8 @@ and the second bank starts after the first. # Flash bank 0 flash bank $_FLASHNAME ambiqmicro 0 0x00040000 0 0 $_TARGETNAME # Flash bank 1 - same size as bank0, starts after bank 0. -flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 $_TARGETNAME +flash bank $_FLASHNAME ambiqmicro 0x00040000 0x00040000 0 0 \ + $_TARGETNAME @end example Flash is programmed using custom entry points into the bootloader. @@ -5177,8 +5240,10 @@ with @code{x} treated as wildcard and otherwise case (and any trailing characters) ignored. @example -flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 $_TARGETNAME S6E2CCAJ0A -flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 $_TARGETNAME S6E2CCAJ0A +flash bank $@{_FLASHNAME@}0 fm4 0x00000000 0 0 0 \ + $_TARGETNAME S6E2CCAJ0A +flash bank $@{_FLASHNAME@}1 fm4 0x00100000 0 0 0 \ + $_TARGETNAME S6E2CCAJ0A @end example @emph{The current implementation is incomplete. Protection is not supported, nor is Chip Erase (only Sector Erase is implemented).} @@ -7403,6 +7468,17 @@ requests by using a special SVC instruction that is trapped at the Supervisor Call vector by OpenOCD. @end deffn +@deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}] +@cindex ARM semihosting +Display status of semihosting fileio, after optionally changing that +status. + +Enabling this option forwards semihosting I/O to GDB process using the +File-I/O remote protocol extension. This is especially useful for +interacting with remote files or displaying console messages in the +debugger. +@end deffn + @section ARMv4 and ARMv5 Architecture @cindex ARMv4 @cindex ARMv5 @@ -7784,13 +7860,14 @@ coprocessor 14 register 7 itself) but all current ARM11 cores @emph{except the ARM1176} use the same six bits. @end deffn -@section ARMv7 Architecture +@section ARMv7 and ARMv8 Architecture @cindex ARMv7 +@cindex ARMv8 -@subsection ARMv7 Debug Access Port (DAP) specific commands +@subsection ARMv7 and ARMv8 Debug Access Port (DAP) specific commands @cindex Debug Access Port @cindex DAP -These commands are specific to ARM architecture v7 Debug Access Port (DAP), +These commands are specific to ARM architecture v7 and v8 Debug Access Port (DAP), included on Cortex-M and Cortex-A systems. They are available in addition to other core-specific commands that may be available. @@ -8044,6 +8121,29 @@ the peripherals. @xref{targetevents,,Target Events}. @end deffn +@subsection ARMv8-A specific commands +@cindex ARMv8-A +@cindex aarch64 + +@deffn Command {aarch64 cache_info} +Display information about target caches +@end deffn + +@deffn Command {aarch64 dbginit} +This command enables debugging by clearing the OS Lock and sticky power-down and reset +indications. It also establishes the expected, basic cross-trigger configuration the aarch64 +target code relies on. In a configuration file, the command would typically be called from a +@code{reset-end} or @code{reset-deassert-post} handler, to re-enable debugging after a system reset. +However, normally it is not necessary to use the command at all. +@end deffn + +@deffn Command {aarch64 smp_on|smp_off} +Enable and disable SMP handling. The state of SMP handling influences the way targets in an SMP group +are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger +halting or resuming of all cores in the group. The command @code{target smp} defines which targets are in the SMP +group. With SMP handling disabled, all targets need to be treated individually. +@end deffn + @section Intel Architecture Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32 @@ -8814,7 +8914,11 @@ end @anchor{gdbrtossupport} OpenOCD includes RTOS support, this will however need enabling as it defaults to disabled. -It can be enabled by passing @option{-rtos} arg to the target @xref{rtostype,,RTOS Type}. +It can be enabled by passing @option{-rtos} arg to the target. @xref{rtostype,,RTOS Type}. + +@xref{Threads, Debugging Programs with Multiple Threads, +Debugging Programs with Multiple Threads, gdb, GDB manual}, for details about relevant +GDB commands. @* An example setup is below: @@ -8833,6 +8937,7 @@ Currently supported rtos's include: @item @option{ChibiOS} @item @option{embKernel} @item @option{mqx} +@item @option{uCOS-III} @end itemize @quotation Note @@ -8866,10 +8971,12 @@ Rtos::sCurrentTask, Rtos::sListReady, Rtos::sListSleep, Rtos::sListSuspended, Rtos::sMaxPriorities, Rtos::sCurrentTaskCount. @item mqx symbols _mqx_kernel_data, MQX_init_struct. +@item uC/OS-III symbols +OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty @end table For most RTOS supported the above symbols will be exported by default. However for -some, eg. FreeRTOS, extra steps must be taken. +some, eg. FreeRTOS and uC/OS-III, extra steps must be taken. These RTOSes may require additional OpenOCD-specific file to be linked along with the project: @@ -8877,6 +8984,8 @@ along with the project: @table @code @item FreeRTOS contrib/rtos-helpers/FreeRTOS-openocd.c +@item uC/OS-III +contrib/rtos-helpers/uCOS-III-openocd.c @end table @node Tcl Scripting API