X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fat91sam7.c;h=cf3547942d39638ac95dd4162327c762b2c67b5c;hp=8a602a3f67c61d7d719649131104850ea1bd90f8;hb=1796e1602e9ffe1cbf35f1b001cb6a534bb2f738;hpb=8b4e882a1630d63bbc9840fa3f968e36b6ac3702 diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c index 8a602a3f67..cf3547942d 100644 --- a/src/flash/at91sam7.c +++ b/src/flash/at91sam7.c @@ -1,7 +1,7 @@ /*************************************************************************** * Copyright (C) 2006 by Magnus Lundin * - * lundin@mlu.mine.nu * - * * + * lundin@mlu.mine.nu * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -33,6 +33,11 @@ There are some things to notice * Lock regions (sectors) are 32 or 64 pages * ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "replacements.h" #include "at91sam7.h" @@ -56,10 +61,11 @@ int at91sam7_erase_check(struct flash_bank_s *bank); int at91sam7_protect_check(struct flash_bank_s *bank); int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size); -u32 at91sam7_get_flash_status(flash_bank_t *bank); -void at91sam7_set_flash_mode(flash_bank_t *bank,int mode); -u8 at91sam7_wait_status_busy(flash_bank_t *bank, int timeout); -int at91sam7_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane); +void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode); +u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout); +int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen); +int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); flash_driver_t at91sam7_flash = { @@ -75,6 +81,9 @@ flash_driver_t at91sam7_flash = .info = at91sam7_info }; +u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 }; +u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 }; +u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 }; char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"}; long NVPSIZ[16] = { @@ -115,52 +124,144 @@ long SRAMSIZ[16] = { 0x80000, /* 512K */ }; -u32 at91sam7_get_flash_status(flash_bank_t *bank) +int at91sam7_register_commands(struct command_context_s *cmd_ctx) { - at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; - long fsr; + command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL); + register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC, + "at91sam7 gpnvm set|clear, set or clear at91sam7 gpnvm bit"); + + return ERROR_OK; +} + +u32 at91sam7_get_flash_status(flash_bank_t *bank, u8 flashplane) +{ + target_t *target = bank->target; + u32 fsr; - target->type->read_memory(target, MC_FSR, 4, 1, (u8 *)&fsr); + target_read_u32(target, MC_FSR[flashplane], &fsr); return fsr; } +/** Read clock configuration and set at91sam7_info->usec_clocks*/ +void at91sam7_read_clock_info(flash_bank_t *bank) +{ + at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; + target_t *target = bank->target; + u32 mckr, mcfr, pllr; + unsigned long tmp = 0, mainfreq; + int flashplane; + + /* Read main clock freqency register */ + target_read_u32(target, CKGR_MCFR, &mcfr); + /* Read master clock register */ + target_read_u32(target, PMC_MCKR, &mckr); + /* Read Clock Generator PLL Register */ + target_read_u32(target, CKGR_PLLR, &pllr); + + at91sam7_info->mck_valid = 0; + switch (mckr & PMC_MCKR_CSS) + { + case 0: /* Slow Clock */ + at91sam7_info->mck_valid = 1; + mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); + tmp = mainfreq; + break; + case 1: /* Main Clock */ + if (mcfr & CKGR_MCFR_MAINRDY) + { + at91sam7_info->mck_valid = 1; + mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); + tmp = mainfreq; + } + break; + + case 2: /* Reserved */ + break; + case 3: /* PLL Clock */ + if (mcfr & CKGR_MCFR_MAINRDY) + { + target_read_u32(target, CKGR_PLLR, &pllr); + if (!(pllr & CKGR_PLLR_DIV)) + break; /* 0 Hz */ + at91sam7_info->mck_valid = 1; + mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff); + /* Integer arithmetic should have sufficient precision + as long as PLL is properly configured. */ + tmp = mainfreq / (pllr & CKGR_PLLR_DIV) * + (((pllr & CKGR_PLLR_MUL) >> 16) + 1); + } + break; + } + + /* Prescaler adjust */ + if (((mckr & PMC_MCKR_PRES) >> 2) == 7) + at91sam7_info->mck_valid = 0; + else + at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2); + + /* Forget old flash timing */ + for (flashplane = 0; flashplanenum_planes; flashplane++) + { + at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NONE); + } +} + /* Setup the timimg registers for nvbits or normal flash */ -void at91sam7_set_flash_mode(flash_bank_t *bank,int mode) +void at91sam7_set_flash_mode(flash_bank_t *bank, u8 flashplane, int mode) { - u32 fmcn, fmr; + u32 fmr, fmcn = 0, fws = 0; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; + target_t *target = bank->target; - if (mode != at91sam7_info->flashmode) { - /* mainf contains the number of main clocks in approx 500uS */ - if (mode==1) - /* main clocks in 1uS */ - fmcn = (at91sam7_info->mainf>>9)+1; - else + if (mode && (mode != at91sam7_info->flashmode[flashplane])) + { + /* Always round up (ceil) */ + if (mode==FMR_TIMING_NVBITS) + { + if (at91sam7_info->cidr_arch == 0x60) + { + /* AT91SAM7A3 uses master clocks in 100 ns */ + fmcn = (at91sam7_info->mck_freq/10000000ul)+1; + } + else + { + /* master clocks in 1uS for ARCH 0x7 types */ + fmcn = (at91sam7_info->mck_freq/1000000ul)+1; + } + } + else if (mode==FMR_TIMING_FLASH) /* main clocks in 1.5uS */ - fmcn = (at91sam7_info->mainf>>9)+(at91sam7_info->mainf>>10)+1; - DEBUG("fmcn: %i", fmcn); - fmr = fmcn<<16; - target->type->write_memory(target, MC_FSR, 4, 1, (u8 *)&fmr); - at91sam7_info->flashmode = mode; + fmcn = (at91sam7_info->mck_freq/666666ul)+1; + + /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */ + if (at91sam7_info->mck_freq <= 33333ul) + fmcn = 0; + /* Only allow fws=0 if clock frequency is < 30 MHz. */ + if (at91sam7_info->mck_freq > 30000000ul) + fws = 1; + + DEBUG("fmcn[%i]: %i", flashplane, fmcn); + fmr = fmcn << 16 | fws << 8; + target_write_u32(target, MC_FMR[flashplane], fmr); } + + at91sam7_info->flashmode[flashplane] = mode; } -u8 at91sam7_wait_status_busy(flash_bank_t *bank, int timeout) +u32 at91sam7_wait_status_busy(flash_bank_t *bank, u8 flashplane, u32 waitbits, int timeout) { u32 status; - while ((!((status = at91sam7_get_flash_status(bank)) & 0x01)) && (timeout-- > 0)) + while ((!((status = at91sam7_get_flash_status(bank,flashplane)) & waitbits)) && (timeout-- > 0)) { - DEBUG("status: 0x%x", status); + DEBUG("status[%i]: 0x%x", flashplane, status); usleep(1000); } - DEBUG("status: 0x%x", status); + DEBUG("status[%i]: 0x%x", flashplane, status); - if (status&0x0C) + if (status & 0x0C) { ERROR("status register: 0x%x", status); if (status & 0x4) @@ -174,20 +275,32 @@ u8 at91sam7_wait_status_busy(flash_bank_t *bank, int timeout) return status; } -int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen) + +/* Send one command to the AT91SAM flash controller */ +int at91sam7_flash_command(struct flash_bank_s *bank, u8 flashplane, u8 cmd, u16 pagen) { u32 fcr; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; + target_t *target = bank->target; - fcr = (0x5A<<24) | (pagen<<8) | cmd; - target->type->write_memory(target, MC_FCR, 4, 1, (u8 *)&fcr); - DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen); + fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd; + target_write_u32(target, MC_FCR[flashplane], fcr); + DEBUG("Flash command: 0x%x, flashplane: %i, pagenumber:%u", fcr, flashplane, pagen); - if (at91sam7_wait_status_busy(bank, 10)&0x0C) + if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB))) + { + /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */ + if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_EOL, 10)&0x0C) + { + return ERROR_FLASH_OPERATION_FAILED; + } + return ERROR_OK; + } + + if (at91sam7_wait_status_busy(bank, flashplane, MC_FSR_FRDY, 10)&0x0C) { return ERROR_FLASH_OPERATION_FAILED; - } + } return ERROR_OK; } @@ -195,16 +308,17 @@ int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen) int at91sam7_read_part_info(struct flash_bank_s *bank) { at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; - unsigned long cidr, mcfr, status; + target_t *target = bank->target; + u32 cidr, status; + int sectornum; - if (at91sam7_info->target->state != TARGET_HALTED) + if (bank->target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } /* Read and parse chip identification register */ - target->type->read_memory(target, DBGU_CIDR, 4, 1, (u8 *)&cidr); + target_read_u32(target, DBGU_CIDR, &cidr); if (cidr == 0) { @@ -222,35 +336,63 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) at91sam7_info->cidr_eproc = (cidr>>5)&0x0007; at91sam7_info->cidr_version = cidr&0x001F; bank->size = NVPSIZ[at91sam7_info->cidr_nvpsiz]; - - DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch ); + at91sam7_info->target_name = "Unknown"; - /* Read main clock freqency register */ - target->type->read_memory(target, CKGR_MCFR, 4, 1, (u8 *)&mcfr); - if (mcfr&0x10000) + /* Support just for bulk erase of a single flash plane, whole device if flash size <= 256k */ + if (NVPSIZ[at91sam7_info->cidr_nvpsiz]<0x80000) /* Flash size less than 512K, one flash plane */ { - at91sam7_info->mainrdy = 1; - at91sam7_info->mainf = mcfr&0xFFFF; - at91sam7_info->usec_clocks = mcfr>>9; - } - else + bank->num_sectors = 1; + bank->sectors = malloc(sizeof(flash_sector_t)); + bank->sectors[0].offset = 0; + bank->sectors[0].size = bank->size; + bank->sectors[0].is_erased = -1; + bank->sectors[0].is_protected = -1; + } + else /* Flash size 512K or larger, several flash planes */ { - at91sam7_info->mainrdy = 0; - at91sam7_info->mainf = 0; - at91sam7_info->usec_clocks = 0; + bank->num_sectors = NVPSIZ[at91sam7_info->cidr_nvpsiz]/0x40000; + bank->sectors = malloc(bank->num_sectors*sizeof(flash_sector_t)); + for (sectornum=0; sectornumnum_sectors; sectornum++) + { + bank->sectors[sectornum].offset = sectornum*0x40000; + bank->sectors[sectornum].size = 0x40000; + bank->sectors[sectornum].is_erased = -1; + bank->sectors[sectornum].is_protected = -1; + } } + + + + DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch ); + + /* Read main and master clock freqency register */ + at91sam7_read_clock_info(bank); - status = at91sam7_get_flash_status(bank); - at91sam7_info->lockbits = status>>16; + at91sam7_info->num_planes = 1; + status = at91sam7_get_flash_status(bank, 0); at91sam7_info->securitybit = (status>>4)&0x01; + at91sam7_protect_check(bank); /* TODO Check the protect check */ - if (at91sam7_info->cidr_arch == 0x70 ) { + if (at91sam7_info->cidr_arch == 0x70 ) + { at91sam7_info->num_nvmbits = 2; at91sam7_info->nvmbits = (status>>8)&0x03; bank->base = 0x100000; bank->bus_width = 4; + if (bank->size==0x80000) /* AT91SAM7S512 */ + { + at91sam7_info->target_name = "AT91SAM7S512"; + at91sam7_info->num_planes = 2; + if (at91sam7_info->num_planes != bank->num_sectors) + WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");; + at91sam7_info->num_lockbits = 2*16; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 64; + at91sam7_info->num_pages = 2*16*64; + } if (bank->size==0x40000) /* AT91SAM7S256 */ { + at91sam7_info->target_name = "AT91SAM7S256"; at91sam7_info->num_lockbits = 16; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -258,6 +400,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) } if (bank->size==0x20000) /* AT91SAM7S128 */ { + at91sam7_info->target_name = "AT91SAM7S128"; at91sam7_info->num_lockbits = 8; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -265,6 +408,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) } if (bank->size==0x10000) /* AT91SAM7S64 */ { + at91sam7_info->target_name = "AT91SAM7S64"; at91sam7_info->num_lockbits = 16; at91sam7_info->pagesize = 128; at91sam7_info->pages_in_lockregion = 32; @@ -272,6 +416,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) } if (bank->size==0x08000) /* AT91SAM7S321/32 */ { + at91sam7_info->target_name = "AT91SAM7S321/32"; at91sam7_info->num_lockbits = 8; at91sam7_info->pagesize = 128; at91sam7_info->pages_in_lockregion = 32; @@ -281,13 +426,26 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) return ERROR_OK; } - if (at91sam7_info->cidr_arch == 0x71 ) { - at91sam7_info->num_nvmbits = 2; - at91sam7_info->nvmbits = (status>>8)&0x03; + if (at91sam7_info->cidr_arch == 0x71 ) + { + at91sam7_info->num_nvmbits = 3; + at91sam7_info->nvmbits = (status>>8)&0x07; bank->base = 0x100000; bank->bus_width = 4; + if (bank->size==0x80000) /* AT91SAM7XC512 */ + { + at91sam7_info->target_name = "AT91SAM7XC512"; + at91sam7_info->num_planes = 2; + if (at91sam7_info->num_planes != bank->num_sectors) + WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");; + at91sam7_info->num_lockbits = 2*16; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 64; + at91sam7_info->num_pages = 2*16*64; + } if (bank->size==0x40000) /* AT91SAM7XC256 */ { + at91sam7_info->target_name = "AT91SAM7XC256"; at91sam7_info->num_lockbits = 16; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -295,6 +453,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) } if (bank->size==0x20000) /* AT91SAM7XC128 */ { + at91sam7_info->target_name = "AT91SAM7XC128"; at91sam7_info->num_lockbits = 8; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -304,13 +463,64 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) return ERROR_OK; } - if (at91sam7_info->cidr_arch == 0x75 ) { + if (at91sam7_info->cidr_arch == 0x72 ) + { + at91sam7_info->num_nvmbits = 2; + at91sam7_info->nvmbits = (status>>8)&0x03; + bank->base = 0x100000; + bank->bus_width = 4; + if (bank->size==0x80000) /* AT91SAM7SE512 */ + { + at91sam7_info->target_name = "AT91SAM7SE512"; + at91sam7_info->num_planes = 2; + if (at91sam7_info->num_planes != bank->num_sectors) + WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");; + at91sam7_info->num_lockbits = 32; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 64; + at91sam7_info->num_pages = 32*64; + } + if (bank->size==0x40000) + { + at91sam7_info->target_name = "AT91SAM7SE256"; + at91sam7_info->num_lockbits = 16; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 64; + at91sam7_info->num_pages = 16*64; + } + if (bank->size==0x08000) + { + at91sam7_info->target_name = "AT91SAM7SE32"; + at91sam7_info->num_lockbits = 8; + at91sam7_info->pagesize = 128; + at91sam7_info->pages_in_lockregion = 32; + at91sam7_info->num_pages = 8*32; + } + + return ERROR_OK; + } + + if (at91sam7_info->cidr_arch == 0x75 ) + { at91sam7_info->num_nvmbits = 3; at91sam7_info->nvmbits = (status>>8)&0x07; bank->base = 0x100000; bank->bus_width = 4; + if (bank->size==0x80000) /* AT91SAM7X512 */ + { + at91sam7_info->target_name = "AT91SAM7X512"; + at91sam7_info->num_planes = 2; + if (at91sam7_info->num_planes != bank->num_sectors) + WARNING("Internal error: Number of flash planes and erase sectors does not match, please report");; + at91sam7_info->num_lockbits = 32; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 64; + at91sam7_info->num_pages = 2*16*64; + DEBUG("Support for AT91SAM7X512 is experimental in this version!"); + } if (bank->size==0x40000) /* AT91SAM7X256 */ { + at91sam7_info->target_name = "AT91SAM7X256"; at91sam7_info->num_lockbits = 16; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -318,6 +528,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) } if (bank->size==0x20000) /* AT91SAM7X128 */ { + at91sam7_info->target_name = "AT91SAM7X128"; at91sam7_info->num_lockbits = 8; at91sam7_info->pagesize = 256; at91sam7_info->pages_in_lockregion = 64; @@ -327,18 +538,32 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) return ERROR_OK; } - if (at91sam7_info->cidr_arch != 0x70 ) + if (at91sam7_info->cidr_arch == 0x60 ) { - WARNING("at91sam7 flash only tested for AT91SAM7Sxx series"); + at91sam7_info->num_nvmbits = 3; + at91sam7_info->nvmbits = (status>>8)&0x07; + bank->base = 0x100000; + bank->bus_width = 4; + + if (bank->size == 0x40000) /* AT91SAM7A3 */ + { + at91sam7_info->target_name = "AT91SAM7A3"; + at91sam7_info->num_lockbits = 16; + at91sam7_info->pagesize = 256; + at91sam7_info->pages_in_lockregion = 16; + at91sam7_info->num_pages = 16*64; + } + return ERROR_OK; } - return ERROR_OK; + + WARNING("at91sam7 flash only tested for AT91SAM7Sxx series"); + + return ERROR_OK; } int at91sam7_erase_check(struct flash_bank_s *bank) { at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; - int i; if (!at91sam7_info->working_area_size) { @@ -353,9 +578,9 @@ int at91sam7_erase_check(struct flash_bank_s *bank) int at91sam7_protect_check(struct flash_bank_s *bank) { u32 status; + int flashplane; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; if (at91sam7_info->cidr == 0) { @@ -367,24 +592,22 @@ int at91sam7_protect_check(struct flash_bank_s *bank) WARNING("Cannot identify target as an AT91SAM"); return ERROR_FLASH_OPERATION_FAILED; } - - status = at91sam7_get_flash_status(bank); - at91sam7_info->lockbits = status>>16; - - return ERROR_OK; -} - - -int at91sam7_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, NULL); + for (flashplane=0;flashplanenum_planes;flashplane++) + { + status = at91sam7_get_flash_status(bank, flashplane); + at91sam7_info->lockbits[flashplane] = (status >> 16); + } + return ERROR_OK; } +/* flash_bank at91sam7 0 0 0 0 + */ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank) { at91sam7_flash_bank_t *at91sam7_info; + int i; if (argc < 6) { @@ -395,16 +618,10 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t)); bank->driver_priv = at91sam7_info; - at91sam7_info->target = get_target_by_num(strtoul(args[5], NULL, 0)); - if (!at91sam7_info->target) - { - ERROR("no target '%i' configured", args[5]); - exit(-1); - } - - /* part wasn't probed for info yet */ at91sam7_info->cidr = 0; + for (i=0;i<4;i++) + at91sam7_info->flashmode[i]=0; return ERROR_OK; } @@ -412,8 +629,9 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch int at91sam7_erase(struct flash_bank_s *bank, int first, int last) { at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - - if (at91sam7_info->target->state != TARGET_HALTED) + u8 flashplane; + + if (bank->target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } @@ -429,29 +647,40 @@ int at91sam7_erase(struct flash_bank_s *bank, int first, int last) return ERROR_FLASH_OPERATION_FAILED; } - if ((first < 0) || (last < first) || (last >= at91sam7_info->num_lockbits)) + if ((first < 0) || (last < first) || (last >= bank->num_sectors)) { - return ERROR_FLASH_SECTOR_INVALID; + if ((first == 0) && (last == (at91sam7_info->num_lockbits-1))) + { + WARNING("Sector numbers based on lockbit count, probably a deprecated script"); + last = bank->num_sectors-1; + } + else return ERROR_FLASH_SECTOR_INVALID; } - if ((first == 0) && (last == (at91sam7_info->num_lockbits-1))) - { - return at91sam7_flash_command(bank, EA, 0); - } - - WARNING("Can only erase the whole flash area, pages are autoerased on write"); - return ERROR_FLASH_OPERATION_FAILED; + /* Configure the flash controller timing */ + at91sam7_read_clock_info(bank); + for (flashplane = first; flashplane<=last; flashplane++) + { + /* Configure the flash controller timing */ + at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH); + if (at91sam7_flash_command(bank, flashplane, EA, 0) != ERROR_OK) + { + return ERROR_FLASH_OPERATION_FAILED; + } + } + return ERROR_OK; + } int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last) { - u32 cmd, pagen, status; + u32 cmd, pagen; + u8 flashplane; int lockregion; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; - if (at91sam7_info->target->state != TARGET_HALTED) + if (bank->target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } @@ -472,24 +701,27 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last) return ERROR_FLASH_OPERATION_FAILED; } - /* Configure the flash controller timing */ - at91sam7_set_flash_mode(bank,1); + at91sam7_read_clock_info(bank); for (lockregion=first;lockregion<=last;lockregion++) { - pagen = lockregion*at91sam7_info->pages_in_lockregion; + pagen = lockregion*at91sam7_info->pages_in_lockregion; + flashplane = (pagen>>10)&0x03; + /* Configure the flash controller timing */ + at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_NVBITS); + if (set) cmd = SLB; else cmd = CLB; - if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK) + + if (at91sam7_flash_command(bank, flashplane, cmd, pagen) != ERROR_OK) { return ERROR_FLASH_OPERATION_FAILED; } } - status = at91sam7_get_flash_status(bank); - at91sam7_info->lockbits = status>>16; + at91sam7_protect_check(bank); return ERROR_OK; } @@ -498,12 +730,12 @@ int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last) int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) { at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - target_t *target = at91sam7_info->target; + target_t *target = bank->target; u32 dst_min_alignment, wcount, bytes_remaining = count; u32 first_page, last_page, pagen, buffer_pos; - u32 fcr; + u8 flashplane; - if (at91sam7_info->target->state != TARGET_HALTED) + if (bank->target->state != TARGET_HALTED) { return ERROR_TARGET_NOT_HALTED; } @@ -530,9 +762,6 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) return ERROR_FLASH_DST_BREAKS_ALIGNMENT; } - if (offset + count > bank->size) - return ERROR_FLASH_DST_OUT_OF_BANK; - if (at91sam7_info->cidr_arch == 0) return ERROR_FLASH_BANK_NOT_PROBED; @@ -541,27 +770,30 @@ int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count) DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count); - /* Configure the flash controller timing */ - at91sam7_set_flash_mode(bank,2); + at91sam7_read_clock_info(bank); - for (pagen=first_page; pagentype->write_memory(target, bank->base, 4, wcount, buffer+buffer_pos); + target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos); + flashplane = (pagen>>10)&0x3; + /* Configure the flash controller timing */ + at91sam7_set_flash_mode(bank, flashplane, FMR_TIMING_FLASH); /* Send Write Page command to Flash Controller */ - if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK) + if (at91sam7_flash_command(bank, flashplane, WP, pagen) != ERROR_OK) { - return ERROR_FLASH_OPERATION_FAILED; - } - DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen); + return ERROR_FLASH_OPERATION_FAILED; + } + DEBUG("Write flash plane:%i page number:%i", flashplane, pagen); } return ERROR_OK; @@ -585,18 +817,16 @@ int at91sam7_probe(struct flash_bank_s *bank) WARNING("Cannot identify target as an AT91SAM"); return ERROR_FLASH_OPERATION_FAILED; } + return ERROR_OK; } int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size) { - int printed; + int printed, flashplane; at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv; - if (at91sam7_info->cidr == 0) - { - at91sam7_read_part_info(bank); - } + at91sam7_read_part_info(bank); if (at91sam7_info->cidr == 0) { @@ -606,20 +836,35 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size) return ERROR_FLASH_OPERATION_FAILED; } - printed = snprintf(buf, buf_size, "\nat91sam7 information:\n"); + printed = snprintf(buf, buf_size, "\nat91sam7 information: Chip is %s\n",at91sam7_info->target_name); buf += printed; buf_size -= printed; - printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x, flashsize: 0x%8.8x\n", at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size); + printed = snprintf(buf, buf_size, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x, flashsize: 0x%8.8x\n", + at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc], at91sam7_info->cidr_version, bank->size); buf += printed; buf_size -= printed; - printed = snprintf(buf, buf_size, "main clock(estimated): %ikHz \n", at91sam7_info->mainf*2); + printed = snprintf(buf, buf_size, "master clock(estimated): %ikHz \n", at91sam7_info->mck_freq / 1000); buf += printed; buf_size -= printed; + if (at91sam7_info->num_planes>1) { + printed = snprintf(buf, buf_size, "flashplanes: %i, pagesize: %i, lock regions: %i, pages in lock region: %i \n", + at91sam7_info->num_planes, at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->num_pages/at91sam7_info->num_lockbits); + buf += printed; + buf_size -= printed; + for (flashplane=0; flashplanenum_planes; flashplane++) + { + printed = snprintf(buf, buf_size, "lockbits[%i]: 0x%4.4x, ", flashplane, at91sam7_info->lockbits[flashplane]); + buf += printed; + buf_size -= printed; + } + } + else if (at91sam7_info->num_lockbits>0) { - printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits,at91sam7_info->num_pages/at91sam7_info->num_lockbits); + printed = snprintf(buf, buf_size, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", + at91sam7_info->pagesize, at91sam7_info->num_lockbits, at91sam7_info->lockbits[0], at91sam7_info->num_pages/at91sam7_info->num_lockbits); buf += printed; buf_size -= printed; } @@ -630,3 +875,92 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size) return ERROR_OK; } + +/* +* On AT91SAM7S: When the gpnmv bits are set with +* > at91sam7 gpnvm 0 bitnr set +* the changes are not visible in the flash controller status register MC_FSR +* until the processor has been reset. +* On the Olimex board this requires a power cycle. +* Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3): +* The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes +* Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit. +*/ +int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +{ + flash_bank_t *bank; + int bit; + u8 flashcmd; + u32 status; + char *value; + at91sam7_flash_bank_t *at91sam7_info; + + if (argc < 3) + { + command_print(cmd_ctx, "at91sam7 gpnvm "); + return ERROR_OK; + } + + bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0)); + bit = atoi(args[1]); + value = args[2]; + + if (!bank) + { + command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]); + return ERROR_OK; + } + + at91sam7_info = bank->driver_priv; + + if (bank->target->state != TARGET_HALTED) + { + return ERROR_TARGET_NOT_HALTED; + } + + if (at91sam7_info->cidr == 0) + { + at91sam7_read_part_info(bank); + } + + if (at91sam7_info->cidr == 0) + { + WARNING("Cannot identify target as an AT91SAM"); + return ERROR_FLASH_OPERATION_FAILED; + } + + if ((bit<0) || (at91sam7_info->num_nvmbits <= bit)) + { + command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[1],at91sam7_info->target_name); + return ERROR_OK; + } + + if (strcmp(value, "set") == 0) + { + flashcmd = SGPB; + } + else if (strcmp(value, "clear") == 0) + { + flashcmd = CGPB; + } + else + { + command_print(cmd_ctx, "usage: at91sam7 gpnvm "); + return ERROR_OK; + } + + /* Configure the flash controller timing */ + at91sam7_read_clock_info(bank); + at91sam7_set_flash_mode(bank, 0, FMR_TIMING_NVBITS); + + if (at91sam7_flash_command(bank, 0, flashcmd, (u16)(bit)) != ERROR_OK) + { + return ERROR_FLASH_OPERATION_FAILED; + } + + status = at91sam7_get_flash_status(bank, 0); + DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd,bit,status); + at91sam7_info->nvmbits = (status>>8)&((1<num_nvmbits)-1); + + return ERROR_OK; +}