X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnand%2Farm_io.c;h=67b15088542362797a4f87c9256f26b6f646e6b3;hp=4c746757cf841b6311411766d4e61f1744aafe94;hb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee;hpb=899c9975e750ff0144d4a4f63e0f2a619c0b0e58 diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c index 4c746757cf..67b1508854 100644 --- a/src/flash/nand/arm_io.c +++ b/src/flash/nand/arm_io.c @@ -17,7 +17,7 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the * Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #ifdef HAVE_CONFIG_H @@ -27,10 +27,10 @@ #include "core.h" #include "arm_io.h" #include -#include +#include +#include #include - /** * Copies code to a working area. This will allocate room for the code plus the * additional amount requested if the working area pointer is null. @@ -43,9 +43,9 @@ * @param area Pointer to a pointer to a working area to copy code to * @return Success or failure of the operation */ -int arm_code_to_working_area(struct target *target, - const uint32_t *code, unsigned code_size, - unsigned additional, struct working_area **area) +static int arm_code_to_working_area(struct target *target, + const uint32_t *code, unsigned code_size, + unsigned additional, struct working_area **area) { uint8_t code_buf[code_size]; unsigned i; @@ -61,7 +61,7 @@ int arm_code_to_working_area(struct target *target, if (NULL == *area) { retval = target_alloc_working_area(target, size, area); if (retval != ERROR_OK) { - LOG_DEBUG("%s: no %d byte buffer", __FUNCTION__, (int) size); + LOG_DEBUG("%s: no %d byte buffer", __func__, (int) size); return ERROR_NAND_NO_BUFFER; } } @@ -79,14 +79,13 @@ int arm_code_to_working_area(struct target *target, /** * ARM-specific bulk write from buffer to address of 8-bit wide NAND. - * For now this only supports ARMv4 and ARMv5 cores. + * For now this supports ARMv4,ARMv5 and ARMv7-M cores. * * Enhancements to target_run_algorithm() could enable: * - ARMv6 and ARMv7 cores in ARM mode * * Different code fragments could handle: - * - Thumb2 cores like Cortex-M (needs different byteswapping) - * - 16-bit wide data (needs different setup too) + * - 16-bit wide data (needs different setup) * * @param nand Pointer to the arm_nand_data struct that defines the I/O * @param data Pointer to the data to be copied to flash @@ -95,20 +94,22 @@ int arm_code_to_working_area(struct target *target, */ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) { - struct target *target = nand->target; - struct arm_algorithm algo; - struct arm *armv4_5 = target->arch_info; - struct reg_param reg_params[3]; - uint32_t target_buf; - uint32_t exit = 0; - int retval; + struct target *target = nand->target; + struct arm_algorithm armv4_5_algo; + struct armv7m_algorithm armv7m_algo; + void *arm_algo; + struct arm *arm = target->arch_info; + struct reg_param reg_params[3]; + uint32_t target_buf; + uint32_t exit_var = 0; + int retval; /* Inputs: * r0 NAND data address (byte wide) * r1 buffer address * r2 buffer length */ - static const uint32_t code[] = { + static const uint32_t code_armv4_5[] = { 0xe4d13001, /* s: ldrb r3, [r1], #1 */ 0xe5c03000, /* strb r3, [r0] */ 0xe2522001, /* subs r2, r2, #1 */ @@ -118,31 +119,55 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) 0xe1200070, /* e: bkpt #0 */ }; + /* Inputs: + * r0 NAND data address (byte wide) + * r1 buffer address + * r2 buffer length + * + * see contrib/loaders/flash/armv7m_io.s for src + */ + static const uint32_t code_armv7m[] = { + 0x3b01f811, + 0x3a017003, + 0xaffaf47f, + 0xbf00be00, + }; + + int target_code_size = 0; + const uint32_t *target_code_src = NULL; + + /* set up algorithm */ + if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */ + armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_algo.core_mode = ARM_MODE_THREAD; + arm_algo = &armv7m_algo; + target_code_size = sizeof(code_armv7m); + target_code_src = code_armv7m; + } else { + armv4_5_algo.common_magic = ARM_COMMON_MAGIC; + armv4_5_algo.core_mode = ARM_MODE_SVC; + armv4_5_algo.core_state = ARM_STATE_ARM; + arm_algo = &armv4_5_algo; + target_code_size = sizeof(code_armv4_5); + target_code_src = code_armv4_5; + } + if (nand->op != ARM_NAND_WRITE || !nand->copy_area) { - retval = arm_code_to_working_area(target, code, sizeof(code), + retval = arm_code_to_working_area(target, target_code_src, target_code_size, nand->chunk_size, &nand->copy_area); - if (retval != ERROR_OK) { + if (retval != ERROR_OK) return retval; - } } nand->op = ARM_NAND_WRITE; /* copy data to work area */ - target_buf = nand->copy_area->address + sizeof(code); - retval = target_bulk_write_memory(target, target_buf, size / 4, data); - if (retval == ERROR_OK && (size & 3) != 0) - retval = target_write_memory(target, - target_buf + (size & ~3), - 1, size & 3, data + (size & ~3)); + target_buf = nand->copy_area->address + target_code_size; + retval = target_write_buffer(target, target_buf, size, data); if (retval != ERROR_OK) return retval; - /* set up algorithm and parameters */ - algo.common_magic = ARM_COMMON_MAGIC; - algo.core_mode = ARM_MODE_SVC; - algo.core_state = ARM_STATE_ARM; - + /* set up parameters */ init_reg_param(®_params[0], "r0", 32, PARAM_IN); init_reg_param(®_params[1], "r1", 32, PARAM_IN); init_reg_param(®_params[2], "r2", 32, PARAM_IN); @@ -152,12 +177,12 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) - exit = nand->copy_area->address + sizeof(code) - 4; + if (arm->is_armv4) + exit_var = nand->copy_area->address + target_code_size - 4; /* use alg to write data from work area to NAND chip */ retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - nand->copy_area->address, exit, 1000, &algo); + nand->copy_area->address, exit_var, 1000, arm_algo); if (retval != ERROR_OK) LOG_ERROR("error executing hosted NAND write"); @@ -180,11 +205,13 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) { struct target *target = nand->target; - struct arm_algorithm algo; - struct arm *armv4_5 = target->arch_info; + struct arm_algorithm armv4_5_algo; + struct armv7m_algorithm armv7m_algo; + void *arm_algo; + struct arm *arm = target->arch_info; struct reg_param reg_params[3]; uint32_t target_buf; - uint32_t exit = 0; + uint32_t exit_var = 0; int retval; /* Inputs: @@ -192,7 +219,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) * r1 NAND data address (byte wide) * r2 buffer length */ - static const uint32_t code[] = { + static const uint32_t code_armv4_5[] = { 0xe5d13000, /* s: ldrb r3, [r1] */ 0xe4c03001, /* strb r3, [r0], #1 */ 0xe2522001, /* subs r2, r2, #1 */ @@ -202,23 +229,51 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) 0xe1200070, /* e: bkpt #0 */ }; + /* Inputs: + * r0 buffer address + * r1 NAND data address (byte wide) + * r2 buffer length + * + * see contrib/loaders/flash/armv7m_io.s for src + */ + static const uint32_t code_armv7m[] = { + 0xf800780b, + 0x3a013b01, + 0xaffaf47f, + 0xbf00be00, + }; + + int target_code_size = 0; + const uint32_t *target_code_src = NULL; + + /* set up algorithm */ + if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */ + armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC; + armv7m_algo.core_mode = ARM_MODE_THREAD; + arm_algo = &armv7m_algo; + target_code_size = sizeof(code_armv7m); + target_code_src = code_armv7m; + } else { + armv4_5_algo.common_magic = ARM_COMMON_MAGIC; + armv4_5_algo.core_mode = ARM_MODE_SVC; + armv4_5_algo.core_state = ARM_STATE_ARM; + arm_algo = &armv4_5_algo; + target_code_size = sizeof(code_armv4_5); + target_code_src = code_armv4_5; + } + /* create the copy area if not yet available */ if (nand->op != ARM_NAND_READ || !nand->copy_area) { - retval = arm_code_to_working_area(target, code, sizeof(code), + retval = arm_code_to_working_area(target, target_code_src, target_code_size, nand->chunk_size, &nand->copy_area); - if (retval != ERROR_OK) { + if (retval != ERROR_OK) return retval; - } } nand->op = ARM_NAND_READ; - target_buf = nand->copy_area->address + sizeof(code); - - /* set up algorithm and parameters */ - algo.common_magic = ARM_COMMON_MAGIC; - algo.core_mode = ARM_MODE_SVC; - algo.core_state = ARM_STATE_ARM; + target_buf = nand->copy_area->address + target_code_size; + /* set up parameters */ init_reg_param(®_params[0], "r0", 32, PARAM_IN); init_reg_param(®_params[1], "r1", 32, PARAM_IN); init_reg_param(®_params[2], "r2", 32, PARAM_IN); @@ -228,12 +283,12 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) - exit = nand->copy_area->address + sizeof(code) - 4; + if (arm->is_armv4) + exit_var = nand->copy_area->address + target_code_size - 4; /* use alg to write data from NAND chip to work area */ retval = target_run_algorithm(target, 0, NULL, 3, reg_params, - nand->copy_area->address, exit, 1000, &algo); + nand->copy_area->address, exit_var, 1000, arm_algo); if (retval != ERROR_OK) LOG_ERROR("error executing hosted NAND read"); @@ -246,4 +301,3 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) return retval; } -