X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91sam3.c;h=a05ab169a07591885b766ef66862d0215569e681;hp=7dbfa24cbf280f2d787d228cbe7515b600180caf;hb=8e44a9663df314ad527cca6687ea362c72e84a3f;hpb=edf0c3376d5394bc05b1028c5a17c19e17657dcb diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c index 7dbfa24cbf..a05ab169a0 100644 --- a/src/flash/nor/at91sam3.c +++ b/src/flash/nor/at91sam3.c @@ -20,7 +20,7 @@ * You should have received a copy of the GNU General public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ****************************************************************************/ /* Some of the the lower level code was based on code supplied by @@ -73,6 +73,11 @@ /* at91sam3s series (has always one flash bank) */ #define FLASH_BANK_BASE_S 0x00400000 +/* at91sam3sd series (has always two flash banks) */ +#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S +#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2)) + + /* at91sam3n series (has always one flash bank) */ #define FLASH_BANK_BASE_N 0x00400000 @@ -82,19 +87,15 @@ #define FLASH_BANK1_BASE_256K_AX 0x000A0000 #define FLASH_BANK1_BASE_512K_AX 0x000C0000 -#define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S -#define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2)) - #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */ #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */ #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */ #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */ -#define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page - * then Lock */ +#define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */ #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */ -/* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */ +/* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */ /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */ -/* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */ +/* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */ /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */ #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */ #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */ @@ -197,7 +198,7 @@ struct sam3_bank_private { /* so we can find the chip we belong to */ struct sam3_chip *pChip; - /* so we can find the orginal bank pointer */ + /* so we can find the original bank pointer */ struct flash_bank *pBank; unsigned bank_number; uint32_t controller_address; @@ -213,7 +214,7 @@ struct sam3_bank_private { struct sam3_chip_details { /* THERE ARE DRAGONS HERE.. */ /* note: If you add pointers here */ - /* becareful about them as they */ + /* be careful about them as they */ /* may need to be updated inside */ /* the function: "sam3_GetDetails() */ /* which copy/overwrites the */ @@ -568,7 +569,7 @@ static const struct sam3_chip_details all_sam3_details[] = { /* Note: The preliminary at91sam3s datasheet says on page 302 */ /* that the flash controller is at address 0x400E0800. */ - /* This is _not_ the case, the controller resides at address 0x400e0a0. */ + /* This is _not_ the case, the controller resides at address 0x400e0a00. */ { .chipid_cidr = 0x28A00960, .name = "at91sam3s4c", @@ -730,6 +731,86 @@ static const struct sam3_chip_details all_sam3_details[] = { }, }, }, + { + .chipid_cidr = 0x298B0A60, + .name = "at91sam3sd8a", + .total_flash_size = 512 * 1024, + .total_sram_size = 64 * 1024, + .n_gpnvms = 3, + .n_banks = 2, + { +/* .bank[0] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_SD, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, +/* .bank[1] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 1, + .base_address = FLASH_BANK1_BASE_512K_SD, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, + }, + }, + { + .chipid_cidr = 0x299B0A60, + .name = "at91sam3sd8b", + .total_flash_size = 512 * 1024, + .total_sram_size = 64 * 1024, + .n_gpnvms = 3, + .n_banks = 2, + { +/* .bank[0] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK0_BASE_SD, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, +/* .bank[1] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 1, + .base_address = FLASH_BANK1_BASE_512K_SD, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 1024, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, + }, + }, { .chipid_cidr = 0x29ab0a60, .name = "at91sam3sd8c", @@ -750,7 +831,7 @@ static const struct sam3_chip_details all_sam3_details[] = { .present = 1, .size_bytes = 256 * 1024, .nsectors = 16, - .sector_size = 16384, + .sector_size = 32768, .page_size = 256, }, /* .bank[1] = { */ @@ -765,7 +846,7 @@ static const struct sam3_chip_details all_sam3_details[] = { .present = 1, .size_bytes = 256 * 1024, .nsectors = 16, - .sector_size = 16384, + .sector_size = 32768, .page_size = 256, }, }, @@ -898,6 +979,102 @@ static const struct sam3_chip_details all_sam3_details[] = { }, }, }, + { + .chipid_cidr = 0x288B0A60, + .name = "at91sam3s8a", + .total_flash_size = 256 * 2048, + .total_sram_size = 64 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +/* .bank[0] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 2048, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, +/* .bank[1] = { */ + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x289B0A60, + .name = "at91sam3s8b", + .total_flash_size = 256 * 2048, + .total_sram_size = 64 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +/* .bank[0] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 2048, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, +/* .bank[1] = { */ + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, + { + .chipid_cidr = 0x28AB0A60, + .name = "at91sam3s8c", + .total_flash_size = 256 * 2048, + .total_sram_size = 64 * 1024, + .n_gpnvms = 2, + .n_banks = 1, + { +/* .bank[0] = { */ + { + .probed = 0, + .pChip = NULL, + .pBank = NULL, + .bank_number = 0, + .base_address = FLASH_BANK_BASE_S, + .controller_address = 0x400e0a00, + .flash_wait_states = 6, /* workaround silicon bug */ + .present = 1, + .size_bytes = 256 * 2048, + .nsectors = 16, + .sector_size = 32768, + .page_size = 256, + }, +/* .bank[1] = { */ + { + .present = 0, + .probed = 0, + .bank_number = 1, + + }, + }, + }, /* Start at91sam3n* series */ { @@ -2156,7 +2333,7 @@ static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip, } /* show the basics */ - LOG_USER_N("\t%*s: %*d [0x%0*x] ", + LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ", REG_NAME_WIDTH, regname, dwidth, v, hwidth, v); @@ -2381,10 +2558,10 @@ static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip) v = (v * pChip->cfg.slow_freq) / 16; pChip->cfg.mainosc_freq = v; - LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)", + LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)", _tomhz(v), - pChip->cfg.slow_freq / 1000, - pChip->cfg.slow_freq % 1000); + (uint32_t)(pChip->cfg.slow_freq / 1000), + (uint32_t)(pChip->cfg.slow_freq % 1000)); } static void sam3_explain_ckgr_plla(struct sam3_chip *pChip) @@ -2400,8 +2577,8 @@ static void sam3_explain_ckgr_plla(struct sam3_chip *pChip) LOG_USER("\tPLLA Freq: (Disabled,mula = 0)"); else if (diva == 0) LOG_USER("\tPLLA Freq: (Disabled,diva = 0)"); - else if (diva == 1) { - pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1)); + else if (diva >= 1) { + pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva); LOG_USER("\tPLLA Freq: %3.03f MHz", _tomhz(pChip->cfg.plla_freq)); } @@ -2554,7 +2731,7 @@ static const struct sam3_reg_list sam3_all_regs[] = { static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank) { - return (struct sam3_bank_private *)(bank->driver_priv); + return bank->driver_priv; } /** @@ -2615,7 +2792,7 @@ static int sam3_ReadAllRegs(struct sam3_chip *pChip) r = sam3_ReadThisReg(pChip, sam3_get_reg_ptr(&(pChip->cfg), pReg)); if (r != ERROR_OK) { - LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d", + LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d", pReg->name, ((unsigned)(pReg->address)), r); return r; } @@ -2654,7 +2831,7 @@ static int sam3_GetInfo(struct sam3_chip *pChip) /* display all regs */ LOG_DEBUG("Start: %s", pReg->name); regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg); - LOG_USER("%*s: [0x%08x] -> 0x%08x", + LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32, REG_NAME_WIDTH, pReg->name, pReg->address, @@ -2670,7 +2847,7 @@ static int sam3_GetInfo(struct sam3_chip *pChip) LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq)); LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq)); - LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x", + LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32, pChip->cfg.unique_id[0], pChip->cfg.unique_id[1], pChip->cfg.unique_id[2], @@ -2825,7 +3002,7 @@ static int sam3_GetDetails(struct sam3_bank_private *pPrivate) LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)", (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR)); /* Help the victim, print details about the chip */ - LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows", + LOG_INFO("SAM3 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows", pPrivate->pChip->cfg.CHIPID_CIDR); sam3_explain_chipid_cidr(pPrivate->pChip); return ERROR_FAIL; @@ -2973,7 +3150,7 @@ static int sam3_erase(struct flash_bank *bank, int first, int last) LOG_DEBUG("Here"); return FLASHD_EraseEntireBank(pPrivate); } - LOG_INFO("sam3 auto-erases while programing (request ignored)"); + LOG_INFO("sam3 auto-erases while programming (request ignored)"); return ERROR_OK; } @@ -3002,23 +3179,13 @@ static int sam3_protect(struct flash_bank *bank, int set, int first, int last) } -static int sam3_info(struct flash_bank *bank, char *buf, int buf_size) -{ - if (bank->target->state != TARGET_HALTED) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; - } - buf[0] = 0; - return ERROR_OK; -} - static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf) { uint32_t adr; int r; adr = pagenum * pPrivate->page_size; - adr += adr + pPrivate->base_address; + adr += pPrivate->base_address; r = target_read_memory(pPrivate->pChip->target, adr, @@ -3126,7 +3293,7 @@ static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, int r; adr = pagenum * pPrivate->page_size; - adr += (adr + pPrivate->base_address); + adr += pPrivate->base_address; /* Get flash mode register value */ r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr); @@ -3556,5 +3723,4 @@ struct flash_driver at91sam3_flash = { .auto_probe = sam3_auto_probe, .erase_check = sam3_erase_check, .protect_check = sam3_protect_check, - .info = sam3_info, };