X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91samd.c;h=9eec0d0ead86b0a0aba89e831067f2a4f508485f;hp=17bc8b99cbcafed2b6bee3a609a32580e99a4576;hb=592d0d514d6602ae9c91cda7e4271c28222a25f6;hpb=b1a1a48b30243d3582a8443f4baf3dd500683eda diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c index 17bc8b99cb..9eec0d0ead 100644 --- a/src/flash/nor/at91samd.c +++ b/src/flash/nor/at91samd.c @@ -27,6 +27,7 @@ #define SAMD_NUM_SECTORS 16 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */ +#define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */ #define SAMD_DSU 0x41002000 /* Device Service Unit */ #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */ @@ -61,6 +62,8 @@ #define SAMD_FAMILY_D 0x00 #define SAMD_SERIES_20 0x00 #define SAMD_SERIES_21 0x01 +#define SAMD_SERIES_10 0x02 +#define SAMD_SERIES_11 0x03 struct samd_part { uint8_t id; @@ -69,6 +72,32 @@ struct samd_part { uint32_t ram_kb; }; +/* Known SAMD10 parts */ +static const struct samd_part samd10_parts[] = { + { 0x0, "SAMD10D14AMU", 16, 4 }, + { 0x1, "SAMD10D13AMU", 8, 4 }, + { 0x2, "SAMD10D12AMU", 4, 4 }, + { 0x3, "SAMD10D14ASU", 16, 4 }, + { 0x4, "SAMD10D13ASU", 8, 4 }, + { 0x5, "SAMD10D12ASU", 4, 4 }, + { 0x6, "SAMD10C14A", 16, 4 }, + { 0x7, "SAMD10C13A", 8, 4 }, + { 0x8, "SAMD10C12A", 4, 4 }, +}; + +/* Known SAMD11 parts */ +static const struct samd_part samd11_parts[] = { + { 0x0, "SAMD11D14AMU", 16, 4 }, + { 0x1, "SAMD11D13AMU", 8, 4 }, + { 0x2, "SAMD11D12AMU", 4, 4 }, + { 0x3, "SAMD11D14ASU", 16, 4 }, + { 0x4, "SAMD11D13ASU", 8, 4 }, + { 0x5, "SAMD11D12ASU", 4, 4 }, + { 0x6, "SAMD11C14A", 16, 4 }, + { 0x7, "SAMD11C13A", 8, 4 }, + { 0x8, "SAMD11C12A", 4, 4 }, +}; + /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */ static const struct samd_part samd20_parts[] = { { 0x0, "SAMD20J18A", 256, 32 }, @@ -81,6 +110,7 @@ static const struct samd_part samd20_parts[] = { { 0x7, "SAMD20G16A", 64, 8 }, { 0x8, "SAMD20G15A", 32, 4 }, { 0x9, "SAMD20G14A", 16, 2 }, + { 0xA, "SAMD20E18A", 256, 32 }, { 0xB, "SAMD20E17A", 128, 16 }, { 0xC, "SAMD20E16A", 64, 8 }, { 0xD, "SAMD20E15A", 32, 4 }, @@ -106,6 +136,17 @@ static const struct samd_part samd21_parts[] = { { 0xE, "SAMD21E14A", 16, 2 }, }; +/* Known SAMR21 parts. */ +static const struct samd_part samr21_parts[] = { + { 0x19, "SAMR21G18A", 256, 32 }, + { 0x1A, "SAMR21G17A", 128, 32 }, + { 0x1B, "SAMR21G16A", 64, 32 }, + { 0x1C, "SAMR21E18A", 256, 32 }, + { 0x1D, "SAMR21E17A", 128, 32 }, + { 0x1E, "SAMR21E16A", 64, 32 }, +}; + + /* Each family of parts contains a parts table in the DEVSEL field of DID. The * processor ID, family ID, and series ID are used to determine which exact * family this is and then we can use the corresponding table. */ @@ -123,6 +164,12 @@ static const struct samd_family samd_families[] = { samd20_parts, ARRAY_SIZE(samd20_parts) }, { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21, samd21_parts, ARRAY_SIZE(samd21_parts) }, + { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21, + samr21_parts, ARRAY_SIZE(samr21_parts) }, + { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10, + samd10_parts, ARRAY_SIZE(samd10_parts) }, + { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11, + samd11_parts, ARRAY_SIZE(samd11_parts) }, }; struct samd_info { @@ -249,47 +296,13 @@ static int samd_probe(struct flash_bank *bank) return ERROR_OK; } -static int samd_protect(struct flash_bank *bank, int set, int first, int last) -{ - int res; - struct samd_info *chip = (struct samd_info *)bank->driver_priv; - - res = ERROR_OK; - - for (int s = first; s <= last; s++) { - if (set != bank->sectors[s].is_protected) { - /* Load an address that is within this sector (we use offset 0) */ - res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, - s * chip->sector_size); - if (res != ERROR_OK) - goto exit; - - /* Tell the controller to lock that sector */ - - uint16_t cmd = (set) ? - SAMD_NVM_CMD(SAMD_NVM_CMD_LR) : - SAMD_NVM_CMD(SAMD_NVM_CMD_UR); - - res = target_write_u16(bank->target, - SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, - cmd); - if (res != ERROR_OK) - goto exit; - } - } -exit: - samd_protect_check(bank); - - return res; -} - -static bool samd_check_error(struct flash_bank *bank) +static bool samd_check_error(struct target *target) { int ret; bool error; uint16_t status; - ret = target_read_u16(bank->target, + ret = target_read_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status); if (ret != ERROR_OK) { LOG_ERROR("Can't read NVM status"); @@ -310,7 +323,7 @@ static bool samd_check_error(struct flash_bank *bank) } /* Clear the error conditions by writing a one to them */ - ret = target_write_u16(bank->target, + ret = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status); if (ret != ERROR_OK) LOG_ERROR("Can't clear NVM error conditions"); @@ -318,25 +331,88 @@ static bool samd_check_error(struct flash_bank *bank) return error; } +static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd) +{ + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + /* Read current configuration. */ + uint16_t tmp = 0; + int res = target_read_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, + &tmp); + if (res != ERROR_OK) + return res; + + /* Set cache disable. */ + res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, + tmp | (1<<18)); + if (res != ERROR_OK) + return res; + + /* Issue the NVM command */ + int res_cmd = target_write_u16(target, + SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd)); + + /* Try to restore configuration, regardless of NVM command write + * status. */ + res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, tmp); + + if (res_cmd != ERROR_OK) + return res_cmd; + + if (res != ERROR_OK) + return res; + + /* Check to see if the NVM command resulted in an error condition. */ + if (samd_check_error(target)) + return ERROR_FAIL; + + return ERROR_OK; +} + +static int samd_protect(struct flash_bank *bank, int set, int first, int last) +{ + int res; + struct samd_info *chip = (struct samd_info *)bank->driver_priv; + + res = ERROR_OK; + + for (int s = first; s <= last; s++) { + if (set != bank->sectors[s].is_protected) { + /* Load an address that is within this sector (we use offset 0) */ + res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, + s * chip->sector_size); + if (res != ERROR_OK) + goto exit; + + /* Tell the controller to lock that sector */ + res = samd_issue_nvmctrl_command(bank->target, + set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR); + if (res != ERROR_OK) + goto exit; + } + } +exit: + samd_protect_check(bank); + + return res; +} + static int samd_erase_row(struct flash_bank *bank, uint32_t address) { int res; - bool error = false; /* Set an address contained in the row to be erased */ res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1); - if (res == ERROR_OK) { - /* Issue the Erase Row command to erase that row */ - res = target_write_u16(bank->target, - SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, - SAMD_NVM_CMD(SAMD_NVM_CMD_ER)); - /* Check (and clear) error conditions */ - error = samd_check_error(bank); - } + /* Issue the Erase Row command to erase that row */ + if (res == ERROR_OK) + res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_ER); - if (res != ERROR_OK || error) { + if (res != ERROR_OK) { LOG_ERROR("Failed to erase row containing %08" PRIx32, address); return ERROR_FAIL; } @@ -442,7 +518,7 @@ static int samd_write_row(struct flash_bank *bank, uint32_t address, return res; } - error = samd_check_error(bank); + error = samd_check_error(bank->target); if (error) return ERROR_FAIL; @@ -606,6 +682,51 @@ COMMAND_HANDLER(samd_handle_info_command) return ERROR_OK; } +COMMAND_HANDLER(samd_handle_chip_erase_command) +{ + struct target *target = get_current_target(CMD_CTX); + + if (target) { + /* Enable access to the DSU by disabling the write protect bit */ + target_write_u32(target, SAMD_PAC1, (1<<1)); + /* Tell the DSU to perform a full chip erase. It takes about 240ms to + * perform the erase. */ + target_write_u8(target, SAMD_DSU, (1<<4)); + + command_print(CMD_CTX, "chip erased"); + } + + return ERROR_OK; +} + +COMMAND_HANDLER(samd_handle_set_security_command) +{ + int res = ERROR_OK; + struct target *target = get_current_target(CMD_CTX); + + if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) { + command_print(CMD_CTX, "supply the \"enable\" argument to proceed."); + return ERROR_COMMAND_SYNTAX_ERROR; + } + + if (target) { + if (target->state != TARGET_HALTED) { + LOG_ERROR("Target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB); + + /* Check (and clear) error conditions */ + if (res == ERROR_OK) + command_print(CMD_CTX, "chip secured on next power-cycle"); + else + command_print(CMD_CTX, "failed to secure chip"); + } + + return res; +} + static const struct command_registration at91samd_exec_command_handlers[] = { { .name = "info", @@ -614,6 +735,22 @@ static const struct command_registration at91samd_exec_command_handlers[] = { .help = "Print information about the current at91samd chip" "and its flash configuration.", }, + { + .name = "chip-erase", + .handler = samd_handle_chip_erase_command, + .mode = COMMAND_EXEC, + .help = "Erase the entire Flash by using the Chip" + "Erase feature in the Device Service Unit (DSU).", + }, + { + .name = "set-security", + .handler = samd_handle_set_security_command, + .mode = COMMAND_EXEC, + .help = "Secure the chip's Flash by setting the Security Bit." + "This makes it impossible to read the Flash contents." + "The only way to undo this is to issue the chip-erase" + "command.", + }, COMMAND_REGISTRATION_DONE };