X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fat91samd.c;h=a4cc51d21d39019eb106296ae1cebb03f269bc49;hp=ece1fd20f6d6d9bf6d3b147264377dd10df55289;hb=33d220d10a069be34095313f51ae22052a079b34;hpb=08607aefc0da2394bcce067989812081f742f5e2;ds=sidebyside

diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index ece1fd20f6..a4cc51d21d 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -63,6 +63,8 @@
 /* Known identifiers */
 #define SAMD_PROCESSOR_M0	0x01
 #define SAMD_FAMILY_D		0x00
+#define SAMD_FAMILY_L		0x01
+#define SAMD_FAMILY_C		0x02
 #define SAMD_SERIES_20		0x00
 #define SAMD_SERIES_21		0x01
 #define SAMD_SERIES_10		0x02
@@ -149,6 +151,51 @@ static const struct samd_part samr21_parts[] = {
 	{ 0x1E, "SAMR21E16A",  64, 32 },
 };
 
+/* Known SAML21 parts. */
+static const struct samd_part saml21_parts[] = {
+	{ 0x00, "SAML21J18A", 256, 32 },
+	{ 0x01, "SAML21J17A", 128, 16 },
+	{ 0x02, "SAML21J16A", 64, 8 },
+	{ 0x05, "SAML21G18A", 256, 32 },
+	{ 0x06, "SAML21G17A", 128, 16 },
+	{ 0x07, "SAML21G16A", 64, 8 },
+	{ 0x0A, "SAML21E18A", 256, 32 },
+	{ 0x0B, "SAML21E17A", 128, 16 },
+	{ 0x0C, "SAML21E16A", 64, 8 },
+	{ 0x0D, "SAML21E15A", 32, 4 },
+};
+
+/* Known SAMC20 parts. */
+static const struct samd_part samc20_parts[] = {
+	{ 0x00, "SAMC20J18A", 256, 32 },
+	{ 0x01, "SAMC20J17A", 128, 16 },
+	{ 0x02, "SAMC20J16A", 64, 8 },
+	{ 0x03, "SAMC20J15A", 32, 4 },
+	{ 0x05, "SAMC20G18A", 256, 32 },
+	{ 0x06, "SAMC20G17A", 128, 16 },
+	{ 0x07, "SAMC20G16A", 64, 8 },
+	{ 0x08, "SAMC20G15A", 32, 4 },
+	{ 0x0A, "SAMC20E18A", 256, 32 },
+	{ 0x0B, "SAMC20E17A", 128, 16 },
+	{ 0x0C, "SAMC20E16A", 64, 8 },
+	{ 0x0D, "SAMC20E15A", 32, 4 },
+};
+
+/* Known SAMC21 parts. */
+static const struct samd_part samc21_parts[] = {
+	{ 0x00, "SAMC21J18A", 256, 32 },
+	{ 0x01, "SAMC21J17A", 128, 16 },
+	{ 0x02, "SAMC21J16A", 64, 8 },
+	{ 0x03, "SAMC21J15A", 32, 4 },
+	{ 0x05, "SAMC21G18A", 256, 32 },
+	{ 0x06, "SAMC21G17A", 128, 16 },
+	{ 0x07, "SAMC21G16A", 64, 8 },
+	{ 0x08, "SAMC21G15A", 32, 4 },
+	{ 0x0A, "SAMC21E18A", 256, 32 },
+	{ 0x0B, "SAMC21E17A", 128, 16 },
+	{ 0x0C, "SAMC21E16A", 64, 8 },
+	{ 0x0D, "SAMC21E15A", 32, 4 },
+};
 
 /* Each family of parts contains a parts table in the DEVSEL field of DID.  The
  * processor ID, family ID, and series ID are used to determine which exact
@@ -173,6 +220,12 @@ static const struct samd_family samd_families[] = {
 		samd10_parts, ARRAY_SIZE(samd10_parts) },
 	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
 		samd11_parts, ARRAY_SIZE(samd11_parts) },
+	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
+		saml21_parts, ARRAY_SIZE(saml21_parts) },
+	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
+		samc20_parts, ARRAY_SIZE(samc20_parts) },
+	{ SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
+		samc21_parts, ARRAY_SIZE(samc21_parts) },
 };
 
 struct samd_info {
@@ -190,8 +243,8 @@ static struct samd_info *samd_chips;
 static const struct samd_part *samd_find_part(uint32_t id)
 {
 	uint8_t processor = (id >> 28);
-	uint8_t family = (id >> 24) & 0x0F;
-	uint8_t series = (id >> 16) & 0xFF;
+	uint8_t family = (id >> 23) & 0x1F;
+	uint8_t series = (id >> 16) & 0x3F;
 	uint8_t devsel = id & 0xFF;
 
 	for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
@@ -658,6 +711,9 @@ static int samd_write_row(struct flash_bank *bank, uint32_t address,
 			return res;
 		}
 
+		/* Access through AHB is stalled while flash is being programmed */
+		usleep(200);
+
 		error = samd_check_error(bank->target);
 		if (error)
 			return ERROR_FAIL;
@@ -973,8 +1029,8 @@ COMMAND_HANDLER(samd_handle_bootloader_command)
 					nb = (2 << (8 - size)) * page_size;
 
 				/* There are 4 pages per row */
-				command_print(CMD_CTX, "Bootloader size is %u bytes (%u rows)",
-					   nb, nb / (page_size * 4));
+				command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
+					   nb, (uint32_t)(nb / (page_size * 4)));
 			}
 		}
 	}