X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fcfi.c;h=04fa83b552f0c54463b3fd19241f422870465efc;hp=248f76005e59ae2de2b8fc62bf58b478f02b4bee;hb=a7479fa89def9d8b1854d629dfdaa0ba17132617;hpb=d0e763ac7ef6aa17b17bd00ccdfbccfb4eacda69 diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index 248f76005e..04fa83b552 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -834,10 +834,13 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command) cfi_info->x16_as_x8 = 0; cfi_info->jedec_probe = 0; cfi_info->not_cfi = 0; + cfi_info->data_swap = 0; for (unsigned i = 6; i < CMD_ARGC; i++) { if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0) cfi_info->x16_as_x8 = 1; + else if (strcmp(CMD_ARGV[i], "data_swap") == 0) + cfi_info->data_swap = 1; else if (strcmp(CMD_ARGV[i], "bus_swap") == 0) bus_swap = 1; else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0) @@ -886,8 +889,8 @@ static int cfi_intel_erase(struct flash_bank *bank, int first, int last) if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" - PRIx32, i, bank->base); + LOG_ERROR("couldn't erase block %i of flash bank at base " + TARGET_ADDR_FMT, i, bank->base); return ERROR_FLASH_OPERATION_FAILED; } } @@ -934,8 +937,8 @@ static int cfi_spansion_erase(struct flash_bank *bank, int first, int last) if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" - PRIx32, i, bank->base); + LOG_ERROR("couldn't erase block %i of flash bank at base " + TARGET_ADDR_FMT, i, bank->base); return ERROR_FLASH_OPERATION_FAILED; } } @@ -1095,11 +1098,6 @@ static int cfi_protect(struct flash_bank *bank, int set, int first, int last) return ERROR_TARGET_NOT_HALTED; } - if ((first < 0) || (last < first) || (last >= bank->num_sectors)) { - LOG_ERROR("Invalid sector range"); - return ERROR_FLASH_SECTOR_INVALID; - } - if (cfi_info->qry[0] != 'Q') return ERROR_FLASH_BANK_NOT_PROBED; @@ -1309,7 +1307,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer, busy_pattern_val = cfi_command_val(bank, 0x80); error_pattern_val = cfi_command_val(bank, 0x7e); - LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, + LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT " and of size 0x%04" PRIx32, source->address, buffer_size); /* Programming main loop */ @@ -1421,50 +1419,50 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t static const uint32_t mips_word_16_code[] = { /* start: */ - MIPS32_LHU(9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */ - MIPS32_ADDI(4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */ - MIPS32_SH(13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */ - MIPS32_SH(15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */ - MIPS32_SH(7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */ - MIPS32_SH(9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */ + MIPS32_LHU(0, 9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */ + MIPS32_ADDI(0, 4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */ + MIPS32_SH(0, 13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */ + MIPS32_SH(0, 15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */ + MIPS32_SH(0, 7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */ + MIPS32_SH(0, 9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */ MIPS32_NOP, /* nop */ /* busy: */ - MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ - MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ - MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ - MIPS32_BNE(11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ - MIPS32_NOP, /* nop */ - - MIPS32_SRL(10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */ - MIPS32_AND(11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */ - MIPS32_BNE(11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */ - MIPS32_NOP, /* nop */ - - MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ - MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ - MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ - MIPS32_BNE(11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ + MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ + MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ + MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ + MIPS32_BNE(0, 11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ + MIPS32_NOP, /* nop */ + + MIPS32_SRL(0, 10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */ + MIPS32_AND(0, 11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */ + MIPS32_BNE(0, 11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */ + MIPS32_NOP, /* nop */ + + MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ + MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ + MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ + MIPS32_BNE(0, 11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ MIPS32_NOP, /* nop */ - MIPS32_XOR(9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */ - MIPS32_BEQ(9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */ + MIPS32_XOR(0, 9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */ + MIPS32_BEQ(0, 9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */ MIPS32_NOP, /* nop */ /* cont: */ - MIPS32_ADDI(6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */ - MIPS32_BNE(6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */ + MIPS32_ADDI(0, 6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */ + MIPS32_BNE(0, 6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */ MIPS32_NOP, /* nop */ - MIPS32_LUI(9, 0), /* lui $t1, 0 */ - MIPS32_ORI(9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */ + MIPS32_LUI(0, 9, 0), /* lui $t1, 0 */ + MIPS32_ORI(0, 9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */ - MIPS32_B(4), /* b done ; goto done */ + MIPS32_B(0, 4), /* b done ; goto done */ MIPS32_NOP, /* nop */ /* cont2: */ - MIPS32_ADDI(5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */ - MIPS32_B(NEG16(33)), /* b start ; goto start */ + MIPS32_ADDI(0, 5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */ + MIPS32_B(0, NEG16(33)), /* b start ; goto start */ MIPS32_NOP, /* nop */ /* done: */ - MIPS32_SDBBP, /* sdbbp ; break(); */ + MIPS32_SDBBP(0), /* sdbbp ; break(); */ }; mips32_info.common_magic = MIPS32_COMMON_MAGIC; @@ -2003,8 +2001,9 @@ static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32, - bank->base, address); + LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT + ", address 0x%" PRIx32, + bank->base, address); return ERROR_FLASH_OPERATION_FAILED; } @@ -2028,9 +2027,9 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word, /* Check for valid range */ if (address & buffermask) { - LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32 - " not aligned to 2^%d boundary", - bank->base, address, cfi_info->max_buf_write_size); + LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%" + PRIx32 " not aligned to 2^%d boundary", + bank->base, address, cfi_info->max_buf_write_size); return ERROR_FLASH_OPERATION_FAILED; } @@ -2058,7 +2057,8 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word, return retval; LOG_ERROR( - "couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32, + "couldn't start buffer write operation at base " TARGET_ADDR_FMT + ", address 0x%" PRIx32, bank->base, address); return ERROR_FLASH_OPERATION_FAILED; @@ -2087,7 +2087,7 @@ static int cfi_intel_write_words(struct flash_bank *bank, const uint8_t *word, if (retval != ERROR_OK) return retval; - LOG_ERROR("Buffer write at base 0x%" PRIx32 + LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT ", address 0x%" PRIx32 " failed.", bank->base, address); return ERROR_FLASH_OPERATION_FAILED; } @@ -2123,7 +2123,7 @@ static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint3 if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't write word at base 0x%" PRIx32 + LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT ", address 0x%" PRIx32, bank->base, address); return ERROR_FLASH_OPERATION_FAILED; } @@ -2149,7 +2149,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word /* Check for valid range */ if (address & buffermask) { - LOG_ERROR("Write address at base 0x%" PRIx32 + LOG_ERROR("Write address at base " TARGET_ADDR_FMT ", address 0x%" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size); return ERROR_FLASH_OPERATION_FAILED; @@ -2195,7 +2195,7 @@ static int cfi_spansion_write_words(struct flash_bank *bank, const uint8_t *word if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't write block at base 0x%" PRIx32 + LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address, bufferwsize); return ERROR_FLASH_OPERATION_FAILED; @@ -2331,6 +2331,8 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of int blk_count; /* number of bus_width bytes for block copy */ uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being *programmed */ + uint8_t *swapped_buffer = NULL; + const uint8_t *real_buffer = NULL; int i; int retval; @@ -2357,8 +2359,14 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of return retval; /* replace only bytes that must be written */ - for (i = align; (i < bank->bus_width) && (count > 0); i++, count--) - current_word[i] = *buffer++; + for (i = align; + (i < bank->bus_width) && (count > 0); + i++, count--) + if (cfi_info->data_swap) + /* data bytes are swapped (reverse endianness) */ + current_word[bank->bus_width - i] = *buffer++; + else + current_word[i] = *buffer++; retval = cfi_write_word(bank, current_word, write_p); if (retval != ERROR_OK) @@ -2366,6 +2374,22 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of write_p += bank->bus_width; } + if (cfi_info->data_swap && count) { + swapped_buffer = malloc(count & ~(bank->bus_width - 1)); + switch (bank->bus_width) { + case 2: + buf_bswap16(swapped_buffer, buffer, + count & ~(bank->bus_width - 1)); + break; + case 4: + buf_bswap32(swapped_buffer, buffer, + count & ~(bank->bus_width - 1)); + break; + } + real_buffer = buffer; + buffer = swapped_buffer; + } + /* handle blocks of bus_size aligned bytes */ blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */ switch (cfi_info->pri_id) { @@ -2435,6 +2459,11 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of return retval; } + if (swapped_buffer) { + buffer = real_buffer + (buffer - swapped_buffer); + free(swapped_buffer); + } + /* return to read array mode, so we can read from flash again for padding */ retval = cfi_reset(bank); if (retval != ERROR_OK) @@ -2451,7 +2480,11 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of /* replace only bytes that must be written */ for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--) - current_word[i] = *buffer++; + if (cfi_info->data_swap) + /* data bytes are swapped (reverse endianness) */ + current_word[bank->bus_width - i] = *buffer++; + else + current_word[i] = *buffer++; retval = cfi_write_word(bank, current_word, write_p); if (retval != ERROR_OK) @@ -3079,7 +3112,7 @@ static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, const void *par cfi_info->buf_write_timeout_typ = 0; } -struct flash_driver cfi_flash = { +const struct flash_driver cfi_flash = { .name = "cfi", .flash_bank_command = cfi_flash_bank_command, .erase = cfi_erase, @@ -3092,4 +3125,5 @@ struct flash_driver cfi_flash = { .erase_check = default_flash_blank_check, .protect_check = cfi_protect_check, .info = get_cfi_info, + .free_driver_priv = default_flash_free_driver_priv, };