X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fcfi.c;h=9fe1173af7572ccbf5504b27125dd5ba8dbb5bbe;hp=ec90d7a2ef2f07dd55ce46709cd3002be18aff61;hb=08d4411b59dd8bd0e7d8009003b71d23acbf6eee;hpb=9d31589d19b1c9c4cbde5c361c046d735c43c215 diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index ec90d7a2ef..9fe1173af7 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -19,7 +19,7 @@ * You should have received a copy of the GNU General Public License * * along with this program; if not, write to the * * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -51,7 +51,7 @@ static struct cfi_unlock_addresses cfi_unlock_addresses[] = { [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa }, }; -/* CFI fixups foward declarations */ +/* CFI fixups forward declarations */ static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param); static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param); static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param); @@ -109,7 +109,6 @@ static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups) } } -/* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */ static inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) { struct cfi_flash_bank *cfi_info = bank->driver_priv; @@ -807,7 +806,7 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command) * - not exceed max value; * - not be null; * - be equal to a power of 2. - * bus must be wide enought to hold one chip */ + * bus must be wide enough to hold one chip */ if ((bank->chip_width > CFI_MAX_CHIP_WIDTH) || (bank->bus_width > CFI_MAX_BUS_WIDTH) || (bank->chip_width == 0) @@ -825,8 +824,6 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command) cfi_info->pri_ext = NULL; bank->driver_priv = cfi_info; - cfi_info->write_algorithm = NULL; - cfi_info->x16_as_x8 = 0; cfi_info->jedec_probe = 0; cfi_info->not_cfi = 0; @@ -838,8 +835,6 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command) cfi_info->jedec_probe = 1; } - cfi_info->write_algorithm = NULL; - /* bank wasn't probed yet */ cfi_info->qry[0] = 0xff; @@ -875,9 +870,8 @@ static int cfi_intel_erase(struct flash_bank *bank, int first, int last) if (retval != ERROR_OK) return retval; - LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, - i, - bank->base); + LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" + PRIx32, i, bank->base); return ERROR_FLASH_OPERATION_FAILED; } } @@ -1143,10 +1137,10 @@ static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd) static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count) { - struct cfi_flash_bank *cfi_info = bank->driver_priv; struct target *target = bank->target; struct reg_param reg_params[7]; struct arm_algorithm arm_algo; + struct working_area *write_algorithm; struct working_area *source = NULL; uint32_t buffer_size = 32768; uint32_t write_command_val, busy_pattern_val, error_pattern_val; @@ -1163,56 +1157,56 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */ static const uint32_t word_32_code[] = { - 0xe4904004, /* loop: ldr r4, [r0], #4 */ - 0xe5813000, /* str r3, [r1] */ - 0xe5814000, /* str r4, [r1] */ - 0xe5914000, /* busy: ldr r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811004, /* add r1, r1 #4 */ - 0xeafffff2, /* b loop */ - 0xeafffffe /* done: b -2 */ + 0xe4904004, /* loop: ldr r4, [r0], #4 */ + 0xe5813000, /* str r3, [r1] */ + 0xe5814000, /* str r4, [r1] */ + 0xe5914000, /* busy: ldr r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811004, /* add r1, r1 #4 */ + 0xeafffff2, /* b loop */ + 0xeafffffe /* done: b -2 */ }; /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */ static const uint32_t word_16_code[] = { - 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */ - 0xe1c130b0, /* strh r3, [r1] */ - 0xe1c140b0, /* strh r4, [r1] */ - 0xe1d140b0, /* busy ldrh r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811002, /* add r1, r1 #2 */ - 0xeafffff2, /* b loop */ + 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */ + 0xe1c130b0, /* strh r3, [r1] */ + 0xe1c140b0, /* strh r4, [r1] */ + 0xe1d140b0, /* busy ldrh r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811002, /* add r1, r1 #2 */ + 0xeafffff2, /* b loop */ 0xeafffffe /* done: b -2 */ }; /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */ static const uint32_t word_8_code[] = { - 0xe4d04001, /* loop: ldrb r4, [r0], #1 */ - 0xe5c13000, /* strb r3, [r1] */ - 0xe5c14000, /* strb r4, [r1] */ - 0xe5d14000, /* busy ldrb r4, [r1] */ - 0xe0047005, /* and r7, r4, r5 */ - 0xe1570005, /* cmp r7, r5 */ - 0x1afffffb, /* bne busy */ - 0xe1140006, /* tst r4, r6 */ - 0x1a000003, /* bne done */ - 0xe2522001, /* subs r2, r2, #1 */ - 0x0a000001, /* beq done */ - 0xe2811001, /* add r1, r1 #1 */ - 0xeafffff2, /* b loop */ - 0xeafffffe /* done: b -2 */ + 0xe4d04001, /* loop: ldrb r4, [r0], #1 */ + 0xe5c13000, /* strb r3, [r1] */ + 0xe5c14000, /* strb r4, [r1] */ + 0xe5d14000, /* busy ldrb r4, [r1] */ + 0xe0047005, /* and r7, r4, r5 */ + 0xe1570005, /* cmp r7, r5 */ + 0x1afffffb, /* bne busy */ + 0xe1140006, /* tst r4, r6 */ + 0x1a000003, /* bne done */ + 0xe2522001, /* subs r2, r2, #1 */ + 0x0a000001, /* beq done */ + 0xe2811001, /* add r1, r1 #1 */ + 0xeafffff2, /* b loop */ + 0xeafffffe /* done: b -2 */ }; uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE]; const uint32_t *target_code_src; @@ -1236,7 +1230,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, * if not we only need target_code_size. */ /* However, we don't want to create multiple code paths, so we - * do the unecessary evaluation of target_code_src, which the + * do the unnecessary evaluation of target_code_src, which the * compiler will probably nicely optimize away if not needed */ /* prepare algorithm code for target endian */ @@ -1260,35 +1254,33 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, } /* flash write code */ - if (!cfi_info->write_algorithm) { - if (target_code_size > sizeof(target_code)) { - LOG_WARNING("Internal error - target code buffer to small. " + if (target_code_size > sizeof(target_code)) { + LOG_WARNING("Internal error - target code buffer to small. " "Increase CFI_MAX_INTEL_CODESIZE and recompile."); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); - /* Get memory for block write handler */ - retval = target_alloc_working_area(target, - target_code_size, - &cfi_info->write_algorithm); - if (retval != ERROR_OK) { - LOG_WARNING("No working area available, can't do block memory writes"); - return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; - } - ; + /* Get memory for block write handler */ + retval = target_alloc_working_area(target, + target_code_size, + &write_algorithm); + if (retval != ERROR_OK) { + LOG_WARNING("No working area available, can't do block memory writes"); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } + ; - /* write algorithm code to working area */ - retval = target_write_buffer(target, cfi_info->write_algorithm->address, - target_code_size, target_code); - if (retval != ERROR_OK) { - LOG_ERROR("Unable to write block write code to target"); - goto cleanup; - } + /* write algorithm code to working area */ + retval = target_write_buffer(target, write_algorithm->address, + target_code_size, target_code); + if (retval != ERROR_OK) { + LOG_ERROR("Unable to write block write code to target"); + goto cleanup; } /* Get a workspace buffer for the data to flash starting with 32k size. - Half size until buffer would be smaller 256 Bytem then fail back */ + * Half size until buffer would be smaller 256 Bytes then fail back */ /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { buffer_size /= 2; @@ -1340,8 +1332,8 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, /* Execute algorithm, assume breakpoint for last instruction */ retval = target_run_algorithm(target, 0, NULL, 7, reg_params, - cfi_info->write_algorithm->address, - cfi_info->write_algorithm->address + target_code_size - + write_algorithm->address, + write_algorithm->address + target_code_size - sizeof(uint32_t), 10000, /* 10s should be enough for max. 32k of data */ &arm_algo); @@ -1361,7 +1353,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, /* Check return value from algo code */ wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val; if (wsm_error) { - /* read status register (outputs debug inforation) */ + /* read status register (outputs debug information) */ uint8_t status; cfi_intel_wait_status_busy(bank, 100, &status); cfi_intel_clear_status_register(bank); @@ -1381,10 +1373,7 @@ cleanup: if (source) target_free_working_area(target, source); - if (cfi_info->write_algorithm) { - target_free_working_area(target, cfi_info->write_algorithm); - cfi_info->write_algorithm = NULL; - } + target_free_working_area(target, write_algorithm); destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]); @@ -1405,6 +1394,7 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffe struct target *target = bank->target; struct reg_param reg_params[10]; struct mips32_algorithm mips32_info; + struct working_area *write_algorithm; struct working_area *source; uint32_t buffer_size = 32768; uint32_t status; @@ -1429,67 +1419,50 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffe static const uint32_t mips_word_16_code[] = { /* start: */ - MIPS32_LHU(9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */ - MIPS32_ADDI(4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */ - MIPS32_SH(13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = - *fl_unl_cmd1 */ - MIPS32_SH(15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = - *fl_unl_cmd2 */ - MIPS32_SH(7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = - *fl_write_cmd */ - MIPS32_SH(9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */ - MIPS32_NOP, /* nop */ + MIPS32_LHU(9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */ + MIPS32_ADDI(4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */ + MIPS32_SH(13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */ + MIPS32_SH(15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */ + MIPS32_SH(7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */ + MIPS32_SH(9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */ + MIPS32_NOP, /* nop */ /* busy: */ - MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ - MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ - *temp1; */ - MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & - *DQ7mask */ - MIPS32_BNE(11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != - *DQ7mask) goto cont */ - MIPS32_NOP, /* nop */ - - MIPS32_SRL(10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> - *2 */ - MIPS32_AND(11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & - *temp1 */ - MIPS32_BNE(11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != - *temp1) goto busy */ - MIPS32_NOP, /* nop */ - - MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ - MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ - *temp1; */ - MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & - *DQ7mask */ - MIPS32_BNE(11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != - *DQ7mask) goto cont */ - MIPS32_NOP, /* nop */ - - MIPS32_XOR(9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */ - MIPS32_BEQ(9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto - *done */ - MIPS32_NOP, /* nop */ + MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ + MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ + MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ + MIPS32_BNE(11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ + MIPS32_NOP, /* nop */ + + MIPS32_SRL(10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */ + MIPS32_AND(11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */ + MIPS32_BNE(11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */ + MIPS32_NOP, /* nop */ + + MIPS32_LHU(10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */ + MIPS32_XOR(11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */ + MIPS32_AND(11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */ + MIPS32_BNE(11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */ + MIPS32_NOP, /* nop */ + + MIPS32_XOR(9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */ + MIPS32_BEQ(9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */ + MIPS32_NOP, /* nop */ /* cont: */ - MIPS32_ADDI(6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */ - MIPS32_BNE(6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) - *goto cont2 */ - MIPS32_NOP, /* nop */ + MIPS32_ADDI(6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */ + MIPS32_BNE(6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */ + MIPS32_NOP, /* nop */ - MIPS32_LUI(9, 0), /* lui $t1, 0 */ - MIPS32_ORI(9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */ + MIPS32_LUI(9, 0), /* lui $t1, 0 */ + MIPS32_ORI(9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */ - MIPS32_B(4), /* b done ; goto done */ - MIPS32_NOP, /* nop */ + MIPS32_B(4), /* b done ; goto done */ + MIPS32_NOP, /* nop */ /* cont2: */ - MIPS32_ADDI(5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */ - MIPS32_B(NEG16(33)), /* b start ; goto start */ - MIPS32_NOP, /* nop */ - /* done: - *MIPS32_B(NEG16(1)), */ /* b done ; goto done */ - MIPS32_SDBBP, /* sdbbp ; break(); */ - /*MIPS32_B(NEG16(33)), */ /* b start ; goto start - * MIPS32_NOP, */ + MIPS32_ADDI(5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */ + MIPS32_B(NEG16(33)), /* b start ; goto start */ + MIPS32_NOP, /* nop */ + /* done: */ + MIPS32_SDBBP, /* sdbbp ; break(); */ }; mips32_info.common_magic = MIPS32_COMMON_MAGIC; @@ -1518,44 +1491,42 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffe } /* flash write code */ - if (!cfi_info->write_algorithm) { - uint8_t *target_code; - - /* convert bus-width dependent algorithm code to correct endiannes */ - target_code = malloc(target_code_size); - if (target_code == NULL) { - LOG_ERROR("Out of memory"); - return ERROR_FAIL; - } - cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); + uint8_t *target_code; - /* allocate working area */ - retval = target_alloc_working_area(target, target_code_size, - &cfi_info->write_algorithm); - if (retval != ERROR_OK) { - free(target_code); - return retval; - } + /* convert bus-width dependent algorithm code to correct endianness */ + target_code = malloc(target_code_size); + if (target_code == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); - /* write algorithm code to working area */ - retval = target_write_buffer(target, cfi_info->write_algorithm->address, - target_code_size, target_code); - if (retval != ERROR_OK) { - free(target_code); - return retval; - } + /* allocate working area */ + retval = target_alloc_working_area(target, target_code_size, + &write_algorithm); + if (retval != ERROR_OK) { + free(target_code); + return retval; + } + /* write algorithm code to working area */ + retval = target_write_buffer(target, write_algorithm->address, + target_code_size, target_code); + if (retval != ERROR_OK) { free(target_code); + return retval; } + + free(target_code); + /* the following code still assumes target code is fixed 24*4 bytes */ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { buffer_size /= 2; if (buffer_size <= 256) { - /* if we already allocated the writing code, but failed to get a + /* we already allocated the writing code, but failed to get a * buffer, free the algorithm */ - if (cfi_info->write_algorithm) - target_free_working_area(target, cfi_info->write_algorithm); + target_free_working_area(target, write_algorithm); LOG_WARNING( "not enough working area available, can't do block memory writes"); @@ -1593,8 +1564,8 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, uint8_t *buffe buf_set_u32(reg_params[9].value, 0, 32, 0x55555555); retval = target_run_algorithm(target, 0, NULL, 10, reg_params, - cfi_info->write_algorithm->address, - cfi_info->write_algorithm->address + ((target_code_size) - 4), + write_algorithm->address, + write_algorithm->address + ((target_code_size) - 4), 10000, &mips32_info); if (retval != ERROR_OK) break; @@ -1634,9 +1605,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext; struct target *target = bank->target; struct reg_param reg_params[10]; - struct arm_algorithm *arm_algo; + void *arm_algo; struct arm_algorithm armv4_5_algo; struct armv7m_algorithm armv7m_algo; + struct working_area *write_algorithm; struct working_area *source; uint32_t buffer_size = 32768; uint32_t status; @@ -1668,8 +1640,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0xe5883000, /* str r3, [r8] */ 0xe5815000, /* str r5, [r1] */ 0xe1a00000, /* nop */ - /* - * 00008110 : */ + /* 00008110 : */ 0xe5916000, /* ldr r6, [r1] */ 0xe0257006, /* eor r7, r5, r6 */ 0xe0147007, /* ands r7, r4, r7 */ @@ -1682,15 +1653,13 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0x0a000001, /* beq 8140 ; b if DQ7 == Data7 */ 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */ 0x1a000004, /* bne 8154 */ - /* - * 00008140 : */ + /* 00008140 : */ 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ 0x03a05080, /* moveq r5, #128 ; 0x80 */ 0x0a000001, /* beq 8154 */ 0xe2811004, /* add r1, r1, #4 ; 0x4 */ 0xeaffffe8, /* b 8100 */ - /* - * 00008154 : */ + /* 00008154 : */ 0xeafffffe /* b 8154 */ }; @@ -1703,8 +1672,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0xe1c830b0, /* strh r3, [r8] */ 0xe1c150b0, /* strh r5, [r1] */ 0xe1a00000, /* nop (mov r0,r0) */ - /* - * 00008168 : */ + /* 00008168 : */ 0xe1d160b0, /* ldrh r6, [r1] */ 0xe0257006, /* eor r7, r5, r6 */ 0xe0147007, /* ands r7, r4, r7 */ @@ -1717,15 +1685,13 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0x0a000001, /* beq 8198 */ 0xe3a05000, /* mov r5, #0 ; 0x0 */ 0x1a000004, /* bne 81ac */ - /* - * 00008198 : */ + /* 00008198 : */ 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ 0x03a05080, /* moveq r5, #128 ; 0x80 */ 0x0a000001, /* beq 81ac */ 0xe2811002, /* add r1, r1, #2 ; 0x2 */ 0xeaffffe8, /* b 8158 */ - /* - * 000081ac : */ + /* 000081ac : */ 0xeafffffe /* b 81ac */ }; @@ -1760,8 +1726,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0xe1c830b0, /* strh r3, [r8] */ 0xe1c150b0, /* strh r5, [r1] */ 0xe1a00000, /* nop (mov r0,r0) */ - /* - * : */ + /* : */ 0xe1d160b0, /* ldrh r6, [r1] */ 0xe0257006, /* eor r7, r5, r6 */ 0xe2177080, /* ands r7, #0x80 */ @@ -1772,8 +1737,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0x0a000001, /* beq 81ac */ 0xe2811002, /* add r1, r1, #2 ; 0x2 */ 0xeafffff0, /* b 8158 */ - /* - * 000081ac : */ + /* 000081ac : */ 0xeafffffe /* b 81ac */ }; @@ -1786,8 +1750,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0xe5c83000, /* strb r3, [r8] */ 0xe5c15000, /* strb r5, [r1] */ 0xe1a00000, /* nop (mov r0,r0) */ - /* - * 000081c0 : */ + /* 000081c0 : */ 0xe5d16000, /* ldrb r6, [r1] */ 0xe0257006, /* eor r7, r5, r6 */ 0xe0147007, /* ands r7, r4, r7 */ @@ -1800,25 +1763,23 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, 0x0a000001, /* beq 81f0 */ 0xe3a05000, /* mov r5, #0 ; 0x0 */ 0x1a000004, /* bne 8204 */ - /* - * 000081f0 : */ + /* 000081f0 : */ 0xe2522001, /* subs r2, r2, #1 ; 0x1 */ 0x03a05080, /* moveq r5, #128 ; 0x80 */ 0x0a000001, /* beq 8204 */ 0xe2811001, /* add r1, r1, #1 ; 0x1 */ 0xeaffffe8, /* b 81b0 */ - /* - * 00008204 : */ + /* 00008204 : */ 0xeafffffe /* b 8204 */ }; if (strncmp(target_type_name(target), "mips_m4k", 8) == 0) return cfi_spansion_write_block_mips(bank, buffer, address, count); - if (is_armv7m(target_to_armv7m(target))) { /* Cortex-M3 target */ + if (is_armv7m(target_to_armv7m(target))) { /* armv7m target */ armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC; - armv7m_algo.core_mode = ARMV7M_MODE_HANDLER; - arm_algo = (struct arm_algorithm *)&armv7m_algo; + armv7m_algo.core_mode = ARM_MODE_THREAD; + arm_algo = &armv7m_algo; } else if (is_arm(target_to_arm(target))) { /* All other ARM CPUs have 32 bit instructions */ armv4_5_algo.common_magic = ARM_COMMON_MAGIC; @@ -1835,7 +1796,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, switch (bank->bus_width) { case 1: - if (arm_algo->common_magic != ARM_COMMON_MAGIC) { + if (is_armv7m(target_to_armv7m(target))) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1845,19 +1806,17 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, case 2: /* Check for DQ5 support */ if (cfi_info->status_poll_mask & (1 << 5)) { - if (arm_algo->common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */ - target_code_src = armv4_5_word_16_code; - target_code_size = sizeof(armv4_5_word_16_code); - } else if (arm_algo->common_magic == ARMV7M_COMMON_MAGIC) { /* - *cortex-m3 - *target - **/ + if (is_armv7m(target_to_armv7m(target))) { + /* armv7m target */ target_code_src = armv7m_word_16_code; target_code_size = sizeof(armv7m_word_16_code); + } else { /* armv4_5 target */ + target_code_src = armv4_5_word_16_code; + target_code_size = sizeof(armv4_5_word_16_code); } } else { /* No DQ5 support. Use DQ7 DATA# polling only. */ - if (arm_algo->common_magic != ARM_COMMON_MAGIC) { + if (is_armv7m(target_to_armv7m(target))) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1866,7 +1825,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, } break; case 4: - if (arm_algo->common_magic != ARM_COMMON_MAGIC) { + if (is_armv7m(target_to_armv7m(target))) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1880,44 +1839,42 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, } /* flash write code */ - if (!cfi_info->write_algorithm) { - uint8_t *target_code; + uint8_t *target_code; - /* convert bus-width dependent algorithm code to correct endiannes */ - target_code = malloc(target_code_size); - if (target_code == NULL) { - LOG_ERROR("Out of memory"); - return ERROR_FAIL; - } - cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); - - /* allocate working area */ - retval = target_alloc_working_area(target, target_code_size, - &cfi_info->write_algorithm); - if (retval != ERROR_OK) { - free(target_code); - return retval; - } + /* convert bus-width dependent algorithm code to correct endianness */ + target_code = malloc(target_code_size); + if (target_code == NULL) { + LOG_ERROR("Out of memory"); + return ERROR_FAIL; + } + cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4); - /* write algorithm code to working area */ - retval = target_write_buffer(target, cfi_info->write_algorithm->address, - target_code_size, target_code); - if (retval != ERROR_OK) { - free(target_code); - return retval; - } + /* allocate working area */ + retval = target_alloc_working_area(target, target_code_size, + &write_algorithm); + if (retval != ERROR_OK) { + free(target_code); + return retval; + } + /* write algorithm code to working area */ + retval = target_write_buffer(target, write_algorithm->address, + target_code_size, target_code); + if (retval != ERROR_OK) { free(target_code); + return retval; } + + free(target_code); + /* the following code still assumes target code is fixed 24*4 bytes */ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) { buffer_size /= 2; if (buffer_size <= 256) { - /* if we already allocated the writing code, but failed to get a + /* we already allocated the writing code, but failed to get a * buffer, free the algorithm */ - if (cfi_info->write_algorithm) - target_free_working_area(target, cfi_info->write_algorithm); + target_free_working_area(target, write_algorithm); LOG_WARNING( "not enough working area available, can't do block memory writes"); @@ -1955,8 +1912,8 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, buf_set_u32(reg_params[9].value, 0, 32, 0x55555555); retval = target_run_algorithm(target, 0, NULL, 10, reg_params, - cfi_info->write_algorithm->address, - cfi_info->write_algorithm->address + ((target_code_size) - 4), + write_algorithm->address, + write_algorithm->address + ((target_code_size) - 4), 10000, arm_algo); if (retval != ERROR_OK) break; @@ -2637,7 +2594,7 @@ static int cfi_probe(struct flash_bank *bank) * a single bus sequence with address = 0x55, data = 0x98 should put * the device into CFI query mode. * - * SST flashes clearly violate this, and we will consider them incompatbile for now + * SST flashes clearly violate this, and we will consider them incompatible for now */ retval = cfi_query_string(bank, 0x55);