X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fmdr.c;h=f3916ded98fe9f4a5e02397fcb167cd0a2960b28;hp=9a19b559bebd3c753bbd895d59d783e1daa46beb;hb=20113201df25475889a3cd9ee22c0397e4fae530;hpb=6581bf5f15f404a9a219cfed8eebced76b4414a5

diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c
index 9a19b559be..f3916ded98 100644
--- a/src/flash/nor/mdr.c
+++ b/src/flash/nor/mdr.c
@@ -22,9 +22,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -173,7 +171,8 @@ static int mdr_erase(struct flash_bank *bank, int first, int last)
 	if (retval != ERROR_OK)
 		goto reset_pg_and_lock;
 
-	if ((first == 0) && (last == (bank->num_sectors - 1))) {
+	if ((first == 0) && (last == (bank->num_sectors - 1)) &&
+		!mdr_info->mem_type) {
 		retval = mdr_mass_erase(bank);
 		goto reset_pg_and_lock;
 	}
@@ -471,6 +470,107 @@ free_buffer:
 	if (new_buffer)
 		free(new_buffer);
 
+	/* read some bytes bytes to flush buffer in flash accelerator.
+	 * See errata for 1986VE1T and 1986VE3. Error 0007 */
+	if ((retval == ERROR_OK) && (!mdr_info->mem_type)) {
+		uint32_t tmp;
+		target_checksum_memory(bank->target, bank->base, 64, &tmp);
+	}
+
+	return retval;
+}
+
+static int mdr_read(struct flash_bank *bank, uint8_t *buffer,
+		    uint32_t offset, uint32_t count)
+{
+	struct target *target = bank->target;
+	struct mdr_flash_bank *mdr_info = bank->driver_priv;
+	int retval, retval2;
+
+	if (!mdr_info->mem_type)
+		return default_flash_read(bank, buffer, offset, count);
+
+	if (bank->target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	if (offset & 0x3) {
+		LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte alignment", offset);
+		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+	}
+
+	if (count & 0x3) {
+		LOG_ERROR("count 0x%" PRIx32 " breaks required 4-byte alignment", count);
+		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+	}
+
+	uint32_t flash_cmd, cur_per_clock;
+
+	retval = target_read_u32(target, MD_PER_CLOCK, &cur_per_clock);
+	if (retval != ERROR_OK)
+		goto err;
+
+	if (!(cur_per_clock & MD_PER_CLOCK_RST_CLK)) {
+		/* Something's very wrong if the RST_CLK module is not clocked */
+		LOG_ERROR("Target needs reset before flash operations");
+		retval = ERROR_FLASH_OPERATION_FAILED;
+		goto err;
+	}
+
+	retval = target_write_u32(target, MD_PER_CLOCK, cur_per_clock | MD_PER_CLOCK_EEPROM);
+	if (retval != ERROR_OK)
+		goto err;
+
+	retval = target_write_u32(target, FLASH_KEY, KEY);
+	if (retval != ERROR_OK)
+		goto err;
+
+	retval = target_read_u32(target, FLASH_CMD, &flash_cmd);
+	if (retval != ERROR_OK)
+		goto err_lock;
+
+	/* Switch on register access */
+	flash_cmd = (flash_cmd & FLASH_DELAY_MASK) | FLASH_CON | FLASH_IFREN;
+	retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+	if (retval != ERROR_OK)
+		goto reset_pg_and_lock;
+
+	for (uint32_t i = 0; i < count; i += 4) {
+		retval = target_write_u32(target, FLASH_ADR, offset + i);
+		if (retval != ERROR_OK)
+			goto reset_pg_and_lock;
+
+		retval = target_write_u32(target, FLASH_CMD, flash_cmd |
+					  FLASH_XE | FLASH_YE | FLASH_SE);
+		if (retval != ERROR_OK)
+			goto reset_pg_and_lock;
+
+		uint32_t buf;
+		retval = target_read_u32(target, FLASH_DO, &buf);
+		if (retval != ERROR_OK)
+			goto reset_pg_and_lock;
+
+		buf_set_u32(buffer, i * 8, 32, buf);
+
+		retval = target_write_u32(target, FLASH_CMD, flash_cmd);
+		if (retval != ERROR_OK)
+			goto reset_pg_and_lock;
+
+	}
+
+reset_pg_and_lock:
+	flash_cmd &= FLASH_DELAY_MASK;
+	retval2 = target_write_u32(target, FLASH_CMD, flash_cmd);
+	if (retval == ERROR_OK)
+		retval = retval2;
+
+err_lock:
+	retval2 = target_write_u32(target, FLASH_KEY, 0);
+	if (retval == ERROR_OK)
+		retval = retval2;
+
+err:
 	return retval;
 }
 
@@ -527,10 +627,11 @@ struct flash_driver mdr_flash = {
 	.erase = mdr_erase,
 	.protect = mdr_protect,
 	.write = mdr_write,
-	.read = default_flash_read,
+	.read = mdr_read,
 	.probe = mdr_probe,
 	.auto_probe = mdr_auto_probe,
 	.erase_check = default_flash_blank_check,
 	.protect_check = mdr_protect_check,
 	.info = get_mdr_info,
+	.free_driver_priv = default_flash_free_driver_priv,
 };