X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fnrf51.c;h=69bf666163ff757a348f9c18ab49d2a435bad179;hp=f078cc3cde12cbee7ad10d7fad950b2400a1ec93;hb=d0e763ac7ef6aa17b17bd00ccdfbccfb4eacda69;hpb=401a2b487613be8f2f39d07a900235dd94d9d73f

diff --git a/src/flash/nor/nrf51.c b/src/flash/nor/nrf51.c
index f078cc3cde..69bf666163 100644
--- a/src/flash/nor/nrf51.c
+++ b/src/flash/nor/nrf51.c
@@ -15,9 +15,7 @@
  *   GNU General Public License for more details.                          *
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -192,6 +190,18 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.build_code	= "G0",
 		.flash_size_kb	= 256,
 	},
+	{
+		.hwid		= 0x0057,
+		.variant	= "QFAA",
+		.build_code	= "G2",
+		.flash_size_kb	= 256,
+	},
+	{
+		.hwid		= 0x0058,
+		.variant	= "QFAA",
+		.build_code	= "G3",
+		.flash_size_kb	= 256,
+	},
 	{
 		.hwid		= 0x004C,
 		.variant	= "QFAB",
@@ -351,15 +361,6 @@ static const struct nrf51_device_spec nrf51_known_devices_table[] = {
 		.flash_size_kb	= 256,
 	},
 
-	/* mdbt40
-	   no idea if variant and build code are correct */
-	{
-		.hwid		= 0x0057,
-		.variant	= "QFAA",
-		.build_code	= "G2",
-		.flash_size_kb	= 256,
-	},
-
 	/* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
 	   with built-in jlink seem to use engineering samples not listed
 	   in the nRF51 Series Compatibility Matrix V1.0. */
@@ -584,7 +585,7 @@ static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
 	if ((ppfc & 0xFF) == 0x00) {
 		LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
 		return ERROR_FAIL;
-	};
+	}
 
 	res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
 			      &clenr0);
@@ -764,7 +765,7 @@ static int nrf51_erase_page(struct flash_bank *bank,
 
 			LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
 			return ERROR_FAIL;
-		};
+		}
 
 		res = nrf51_nvmc_generic_erase(chip,
 					       NRF51_NVMC_ERASEUICR,
@@ -1145,7 +1146,7 @@ COMMAND_HANDLER(nrf51_handle_mass_erase_command)
 		LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
 			  "mass erase command won't work.");
 		return ERROR_FAIL;
-	};
+	}
 
 	res = nrf51_erase_all(chip);
 	if (res != ERROR_OK) {