X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f1x.c;h=e4fcca07fb1e0a5332bbea88a2e5050d10f97d75;hp=66a0ee54b7f274b344b4b427defc1555ba06fddd;hb=5b38f862f8be08cb7163bfe7fe101e4086752fbd;hpb=2493671e2d9c352ea70edc8665b4c8f172ef1141
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 66a0ee54b7..e4fcca07fb 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -130,7 +130,7 @@ struct stm32x_flash_bank {
static int stm32x_mass_erase(struct flash_bank *bank);
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
-static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count);
/* flash bank stm32x 0 0
@@ -150,9 +150,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
stm32x_info->register_base = FLASH_REG_BASE_B0;
stm32x_info->user_bank_size = bank->size;
- /* the stm32l erased value is 0x00 */
- bank->default_padded_value = 0x00;
-
return ERROR_OK;
}
@@ -564,7 +561,7 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
return stm32x_write_options(bank);
}
-static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
@@ -626,7 +623,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
};
retval = target_write_buffer(target, write_algorithm->address,
- sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
+ sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
if (retval != ERROR_OK)
return retval;
@@ -695,7 +692,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
return retval;
}
-static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
+static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
@@ -723,7 +720,7 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
}
LOG_INFO("odd number of bytes to write, padding with 0xff");
buffer = memcpy(new_buffer, buffer, count);
- buffer[count++] = 0xff;
+ new_buffer[count++] = 0xff;
}
uint32_t words_remaining = count / 2;
@@ -897,7 +894,7 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 128;
break;
- case 0x422: /* stm32f30x */
+ case 0x422: /* stm32f302xb/c */
page_size = 2048;
stm32x_info->ppage_size = 2;
max_flash_size_in_kb = 256;
@@ -924,8 +921,18 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->option_offset = 6;
stm32x_info->default_rdp = 0x55AA;
break;
- case 0x440: /* stm32f0x */
- case 0x444:
+ case 0x438: /* stm32f33x */
+ case 0x439: /* stm32f302x6/8 */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 64;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0x55AA;
+ break;
+ case 0x440: /* stm32f05x */
+ case 0x444: /* stm32f03x */
+ case 0x445: /* stm32f04x */
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 64;
@@ -933,6 +940,22 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->option_offset = 6;
stm32x_info->default_rdp = 0x55AA;
break;
+ case 0x448: /* stm32f07x */
+ page_size = 2048;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 128;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0x55AA;
+ break;
+ case 0x442: /* stm32f09x */
+ page_size = 2048;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 256;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0x55AA;
+ break;
default:
LOG_WARNING("Cannot identify target as a STM32 family.");
return ERROR_FAIL;
@@ -1017,6 +1040,21 @@ COMMAND_HANDLER(stm32x_handle_part_id_command)
}
#endif
+static const char *get_stm32f0_revision(uint16_t rev_id)
+{
+ const char *rev_str = NULL;
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "1.0";
+ break;
+ case 0x2000:
+ rev_str = "2.0";
+ break;
+ }
+ return rev_str;
+}
+
static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
{
uint32_t dbgmcu_idcode;
@@ -1111,7 +1149,7 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
break;
case 0x422:
- device_str = "STM32F30x";
+ device_str = "STM32F302xB/C";
switch (rev_id) {
case 0x1000:
@@ -1170,21 +1208,55 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
}
break;
- case 0x440:
- case 0x444:
- device_str = "STM32F0xx";
+ case 0x438:
+ device_str = "STM32F33x";
switch (rev_id) {
case 0x1000:
- rev_str = "1.0";
+ rev_str = "A";
break;
+ }
+ break;
- case 0x2000:
- rev_str = "2.0";
+ case 0x439:
+ device_str = "STM32F302x6/8";
+
+ switch (rev_id) {
+ case 0x1000:
+ rev_str = "A";
+ break;
+
+ case 0x1001:
+ rev_str = "Z";
break;
}
break;
+ case 0x444:
+ device_str = "STM32F03x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x440:
+ device_str = "STM32F05x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x445:
+ device_str = "STM32F04x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x448:
+ device_str = "STM32F07x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
+ case 0x442:
+ device_str = "STM32F09x";
+ rev_str = get_stm32f0_revision(rev_id);
+ break;
+
default:
snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
return ERROR_FAIL;
@@ -1316,10 +1388,10 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
int user_data = optionbyte;
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
+ if (optionbyte >> OPT_ERROR & 1)
command_print(CMD_CTX, "Option Byte Complement Error");
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
+ if (optionbyte >> OPT_READOUT & 1)
command_print(CMD_CTX, "Readout Protection On");
else
command_print(CMD_CTX, "Readout Protection Off");
@@ -1327,32 +1399,32 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
/* user option bytes are offset depending on variant */
optionbyte >>= stm32x_info->option_offset;
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
+ if (optionbyte >> OPT_RDWDGSW & 1)
command_print(CMD_CTX, "Software Watchdog");
else
command_print(CMD_CTX, "Hardware Watchdog");
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
+ if (optionbyte >> OPT_RDRSTSTOP & 1)
command_print(CMD_CTX, "Stop: No reset generated");
else
command_print(CMD_CTX, "Stop: Reset generated");
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
+ if (optionbyte >> OPT_RDRSTSTDBY & 1)
command_print(CMD_CTX, "Standby: No reset generated");
else
command_print(CMD_CTX, "Standby: Reset generated");
if (stm32x_info->has_dual_banks) {
- if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
+ if (optionbyte >> OPT_BFB2 & 1)
command_print(CMD_CTX, "Boot: Bank 0");
else
command_print(CMD_CTX, "Boot: Bank 1");
}
command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
- (user_data >> stm32x_info->user_data_offset) & 0xff);
+ (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
- (user_data >> (stm32x_info->user_data_offset + 8)) & 0xff);
+ (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
return ERROR_OK;
}
@@ -1401,12 +1473,12 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
optionbyte &= ~(1 << 0);
else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
- optionbyte &= ~(1 << 1);
- else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 1);
+ else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
optionbyte &= ~(1 << 1);
else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
- optionbyte &= ~(1 << 2);
- else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
+ optionbyte |= (1 << 2);
+ else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
optionbyte &= ~(1 << 2);
else if (stm32x_info->has_dual_banks) {
if (strcmp("BOOT0", CMD_ARGV[0]) == 0)