X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f1x.c;h=f05a4aaa3f8a4d4df3d2edbd594bc5ccebaa1b6b;hp=f735a7d2e859dbaf292c865eba9ddba5c09b1f65;hb=f9ea791e9b89bed91200f27202f9a95dd4e8640b;hpb=bee7184ce4bd2beb10fb29d1b6ba4e4b33f1c2ed

diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index f735a7d2e8..f05a4aaa3f 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -701,13 +701,13 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
 		if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
 			LOG_ERROR("flash memory not erased before writing");
 			/* Clear but report errors */
-			target_write_u32(target, STM32_FLASH_SR_B0, FLASH_PGERR);
+			target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
 		}
 
 		if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
 			LOG_ERROR("flash memory write protected");
 			/* Clear but report errors */
-			target_write_u32(target, STM32_FLASH_SR_B0, FLASH_WRPRTERR);
+			target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
 		}
 	}
 
@@ -807,7 +807,7 @@ static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
 			return retval;
 	}
 
-	return target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
+	return target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
 }
 
 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
@@ -843,9 +843,35 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
 	return retval;
 }
 
-static int stm32x_probe(struct flash_bank *bank)
+static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
 {
 	struct target *target = bank->target;
+	uint32_t cpuid, flash_size_reg;
+
+	int retval = target_read_u32(target, 0xE000ED00, &cpuid);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (((cpuid >> 4) & 0xFFF) == 0xC20) {
+		/* 0xC20 is M0 devices */
+		flash_size_reg = 0x1FFFF7CC;
+	} else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
+		/* 0xC23 is M3 devices */
+		flash_size_reg = 0x1FFFF7E0;
+	} else {
+		LOG_ERROR("Cannot identify target as a stm32x");
+		return ERROR_FAIL;
+	}
+
+	retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return retval;
+}
+
+static int stm32x_probe(struct flash_bank *bank)
+{
 	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 	int i;
 	uint16_t flash_size_in_kb;
@@ -853,7 +879,6 @@ static int stm32x_probe(struct flash_bank *bank)
 	int page_size;
 	uint32_t base_address = 0x08000000;
 
-
 	stm32x_info->probed = 0;
 	stm32x_info->register_base = FLASH_REG_BASE_B0;
 
@@ -865,7 +890,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
 
 	/* get flash size from target. */
-	retval = target_read_u16(target, 0x1FFFF7E0, &flash_size_in_kb);
+	retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
 	if (retval != ERROR_OK) {
 		LOG_WARNING("failed reading flash size, default to max target family");
 		/* failed reading flash size, default to max target family */
@@ -1176,7 +1201,11 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
 
 		switch (device_id >> 16) {
 			case 0x1000:
-				snprintf(buf, buf_size, "A");
+				snprintf(buf, buf_size, "1.0");
+				break;
+
+			case 0x2000:
+				snprintf(buf, buf_size, "2.0");
 				break;
 
 			default:
@@ -1540,7 +1569,7 @@ struct flash_driver stm32f1x_flash = {
 	.read = default_flash_read,
 	.probe = stm32x_probe,
 	.auto_probe = stm32x_auto_probe,
-	.erase_check = default_flash_mem_blank_check,
+	.erase_check = default_flash_blank_check,
 	.protect_check = stm32x_protect_check,
 	.info = get_stm32x_info,
 };