X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=blobdiff_plain;f=src%2Fflash%2Fnor%2Fstm32f2x.c;h=672f08747331c4e3e32aabd8795b719e8b1bcbec;hp=5f5bfb853aa5f01d6a1a8908fb2fe861ca20b661;hb=977db554c441a7677272aa92e1e18dc29aef1c5a;hpb=055abd0b9cb3427fb9b52263d2be49620e8e4c97
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 5f5bfb853a..672f087473 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -91,70 +91,69 @@
#define FLASH_ERASE_TIMEOUT 10000
#define FLASH_WRITE_TIMEOUT 5
-#define STM32_FLASH_BASE 0x40023c00
-#define STM32_FLASH_ACR 0x40023c00
-#define STM32_FLASH_KEYR 0x40023c04
-#define STM32_FLASH_OPTKEYR 0x40023c08
-#define STM32_FLASH_SR 0x40023c0C
-#define STM32_FLASH_CR 0x40023c10
-#define STM32_FLASH_OPTCR 0x40023c14
-#define STM32_FLASH_OBR 0x40023c1C
+#define STM32_FLASH_BASE 0x40023c00
+#define STM32_FLASH_ACR 0x40023c00
+#define STM32_FLASH_KEYR 0x40023c04
+#define STM32_FLASH_OPTKEYR 0x40023c08
+#define STM32_FLASH_SR 0x40023c0C
+#define STM32_FLASH_CR 0x40023c10
+#define STM32_FLASH_OPTCR 0x40023c14
+#define STM32_FLASH_OBR 0x40023c1C
/* option byte location */
-#define STM32_OB_RDP 0x1FFFF800
-#define STM32_OB_USER 0x1FFFF802
-#define STM32_OB_DATA0 0x1FFFF804
-#define STM32_OB_DATA1 0x1FFFF806
-#define STM32_OB_WRP0 0x1FFFF808
-#define STM32_OB_WRP1 0x1FFFF80A
-#define STM32_OB_WRP2 0x1FFFF80C
-#define STM32_OB_WRP3 0x1FFFF80E
+#define STM32_OB_RDP 0x1FFFF800
+#define STM32_OB_USER 0x1FFFF802
+#define STM32_OB_DATA0 0x1FFFF804
+#define STM32_OB_DATA1 0x1FFFF806
+#define STM32_OB_WRP0 0x1FFFF808
+#define STM32_OB_WRP1 0x1FFFF80A
+#define STM32_OB_WRP2 0x1FFFF80C
+#define STM32_OB_WRP3 0x1FFFF80E
/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_SER (1 << 1)
-#define FLASH_MER (1 << 2)
-#define FLASH_STRT (1 << 16)
-#define FLASH_PSIZE_8 (0 << 8)
-#define FLASH_PSIZE_16 (1 << 8)
-#define FLASH_PSIZE_32 (2 << 8)
-#define FLASH_PSIZE_64 (3 << 8)
-#define FLASH_SNB(a) ((a) << 3)
-#define FLASH_LOCK (1 << 31)
+#define FLASH_PG (1 << 0)
+#define FLASH_SER (1 << 1)
+#define FLASH_MER (1 << 2)
+#define FLASH_MER1 (1 << 15)
+#define FLASH_STRT (1 << 16)
+#define FLASH_PSIZE_8 (0 << 8)
+#define FLASH_PSIZE_16 (1 << 8)
+#define FLASH_PSIZE_32 (2 << 8)
+#define FLASH_PSIZE_64 (3 << 8)
+#define FLASH_SNB(a) ((a) << 3)
+#define FLASH_LOCK (1 << 31)
/* FLASH_SR register bits */
-#define FLASH_BSY (1 << 16)
-#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-#define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
-#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR (1 << 4) /* Write protection error */
-#define FLASH_OPERR (1 << 1) /* Operation error */
+#define FLASH_BSY (1 << 16)
+#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
+#define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
+#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
+#define FLASH_WRPERR (1 << 4) /* Write protection error */
+#define FLASH_OPERR (1 << 1) /* Operation error */
#define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
/* STM32_FLASH_OBR bit definitions (reading) */
-#define OPT_ERROR 0
-#define OPT_READOUT 1
-#define OPT_RDWDGSW 2
-#define OPT_RDRSTSTOP 3
-#define OPT_RDRSTSTDBY 4
-#define OPT_BFB2 5 /* dual flash bank only */
+#define OPT_ERROR 0
+#define OPT_READOUT 1
+#define OPT_RDWDGSW 2
+#define OPT_RDRSTSTOP 3
+#define OPT_RDRSTSTDBY 4
+#define OPT_BFB2 5 /* dual flash bank only */
/* register unlock keys */
-#define KEY1 0x45670123
-#define KEY2 0xCDEF89AB
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
struct stm32x_flash_bank {
- struct working_area *write_algorithm;
int probed;
};
-
/* flash bank stm32x 0 0
*/
FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
@@ -167,7 +166,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
bank->driver_priv = stm32x_info;
- stm32x_info->write_algorithm = NULL;
stm32x_info->probed = 0;
return ERROR_OK;
@@ -316,9 +314,9 @@ static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
uint32_t offset, uint32_t count)
{
- struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
@@ -366,12 +364,12 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
};
if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
- &stm32x_info->write_algorithm) != ERROR_OK) {
+ &write_algorithm) != ERROR_OK) {
LOG_WARNING("no working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- retval = target_write_buffer(target, stm32x_info->write_algorithm->address,
+ retval = target_write_buffer(target, write_algorithm->address,
sizeof(stm32x_flash_write_code),
(uint8_t *)stm32x_flash_write_code);
if (retval != ERROR_OK)
@@ -381,10 +379,9 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
buffer_size /= 2;
if (buffer_size <= 256) {
- /* if we already allocated the writing code, but failed to get a
+ /* we already allocated the writing code, but failed to get a
* buffer, free the algorithm */
- if (stm32x_info->write_algorithm)
- target_free_working_area(target, stm32x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
LOG_WARNING("no large enough working area available, can't do block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -410,7 +407,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
0, NULL,
5, reg_params,
source->address, source->size,
- stm32x_info->write_algorithm->address, 0,
+ write_algorithm->address, 0,
&armv7m_info);
if (retval == ERROR_FLASH_OPERATION_FAILED) {
@@ -430,7 +427,7 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
}
target_free_working_area(target, source);
- target_free_working_area(target, stm32x_info->write_algorithm);
+ target_free_working_area(target, write_algorithm);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
@@ -586,6 +583,7 @@ static int stm32x_probe(struct flash_bank *bank)
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
int i;
uint16_t flash_size_in_kb;
+ uint16_t max_flash_size_in_kb;
uint32_t device_id;
uint32_t base_address = 0x08000000;
@@ -597,36 +595,29 @@ static int stm32x_probe(struct flash_bank *bank)
return retval;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
- /* get flash size from target. */
- retval = target_read_u16(target, 0x1FFF7A22, &flash_size_in_kb);
- if (retval != ERROR_OK) {
- LOG_WARNING("failed reading flash size, default to max target family");
- /* failed reading flash size, default to max target family */
- flash_size_in_kb = 0xffff;
+ /* set max flash size depending on family */
+ switch (device_id & 0xfff) {
+ case 0x411:
+ case 0x413:
+ max_flash_size_in_kb = 1024;
+ break;
+ case 0x419:
+ max_flash_size_in_kb = 2048;
+ break;
+ default:
+ LOG_WARNING("Cannot identify target as a STM32 family.");
+ return ERROR_FAIL;
}
- /* some variants read 0 for flash size register
- * use a max flash size as a default */
- if (flash_size_in_kb == 0)
- flash_size_in_kb = 0xffff;
+ /* get flash size from target. */
+ retval = target_read_u16(target, 0x1FFF7A22, &flash_size_in_kb);
- if ((device_id & 0xfff) == 0x411) {
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff) {
- /* number of sectors may be incorrrect on early silicon */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
- flash_size_in_kb = 1024;
- }
- } else if ((device_id & 0xfff) == 0x413) {
- /* check for early silicon */
- if (flash_size_in_kb == 0xffff) {
- /* number of sectors may be incorrrect on early silicon */
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming 1024k flash");
- flash_size_in_kb = 1024;
- }
- } else {
- LOG_WARNING("Cannot identify target as a STM32 family.");
- return ERROR_FAIL;
+ /* failed reading flash size or flash size invalid (early silicon),
+ * default to max target family */
+ if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
+ max_flash_size_in_kb);
+ flash_size_in_kb = max_flash_size_in_kb;
}
LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
@@ -637,6 +628,10 @@ static int stm32x_probe(struct flash_bank *bank)
/* calculate numbers of pages */
int num_pages = (flash_size_in_kb / 128) + 4;
+ /* check for larger 2048 bytes devices */
+ if (flash_size_in_kb > 1024)
+ num_pages += 4;
+
/* check that calculation result makes sense */
assert(num_pages > 0);
@@ -655,7 +650,17 @@ static int stm32x_probe(struct flash_bank *bank)
setup_sector(bank, 4, 1, 64 * 1024);
/* dynamic memory */
- setup_sector(bank, 4 + 1, num_pages - 5, 128 * 1024);
+ setup_sector(bank, 4 + 1, MAX(12, num_pages) - 5, 128 * 1024);
+
+ if (num_pages > 12) {
+
+ /* fixed memory for larger devices */
+ setup_sector(bank, 12, 4, 16 * 1024);
+ setup_sector(bank, 16, 1, 64 * 1024);
+
+ /* dynamic memory for larger devices */
+ setup_sector(bank, 16 + 1, num_pages - 5 - 12, 128 * 1024);
+ }
for (i = 0; i < num_pages; i++) {
bank->sectors[i].is_erased = -1;
@@ -707,11 +712,16 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
snprintf(buf, buf_size, "Y");
break;
+ case 0x2003:
+ snprintf(buf, buf_size, "X");
+ break;
+
default:
snprintf(buf, buf_size, "unknown");
break;
}
- } else if ((device_id & 0xfff) == 0x413) {
+ } else if (((device_id & 0xfff) == 0x413) ||
+ ((device_id & 0xfff) == 0x419)) {
printed = snprintf(buf, buf_size, "stm32f4x - Rev: ");
buf += printed;
buf_size -= printed;
@@ -752,7 +762,10 @@ static int stm32x_mass_erase(struct flash_bank *bank)
return retval;
/* mass erase flash memory */
- retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
+ if (bank->num_sectors > 12)
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER | FLASH_MER1);
+ else
+ retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),